MC68HC908GR8 Datasheet, PDF (244/286 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Timer Interface Module (TIM)
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered
PWM signals to 100%. As . CHxMAX Latency shows, the CHxMAX bit takes effect in the cycle after it
is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.
NOTE
The 100% PWM duty cycle is defined as a continuous high level if the PWM
polarity is 1 and a continuous low level if the PWM polarity is 0.
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
PTEx/TCHx
PERIOD
CHxMAX
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 22-11. CHxMAX Latency
22.9.5 TIM Channel Registers
These read/write registers contain the captured TIM counter value of the input capture function or the
output compare value of the output compare function. The state of the TIM channel registers after reset
is unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH)
inhibits input captures until the low byte (TCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM channel x registers
(TCHxH) inhibits output compares until the low byte (TCHxL) is written.
Address: T1CH0H, $0026 and T2CH0H, $0031
Bit 7
6
5
4
3
2
Read:
Bit 15
14
13
12
11
10
Write:
Reset:
Indeterminate after reset
1
Bit 0
9
Bit 8
Figure 22-12. TIM Channel 0 Register High (TCH0H)
Address: T1CH0L, $0027 and T2CH0L $0032
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
6
Write:
Reset:
5
4
3
2
Indeterminate after reset
1
Bit 0
Figure 22-13. TIM Channel 0 Register Low (TCH0L)
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7
244
Freescale Semiconductor