MC68HC908GR8 Datasheet, PDF (227/286 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Timebase Register Description
If the timebase functions are not required during stop mode, reduce the power consumption by stopping
the timebase before enabling the STOP instruction.
21.6 Timebase Register Description
The timebase has one register, the TBCR, which is used to enable the timebase interrupts and set the
rate.
Address: $001C
Bit 7
6
5
4
3
2
1
Bit 0
Read: TBIF
0
TBR2
TBR1
TBR0
TBIE
TBON
R
Write:
TACK
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
R = Reserved
Figure 21-2. Timebase Control Register (TBCR)
TBIF — Timebase Interrupt Flag
This read-only flag bit is set when the timebase counter has rolled over.
1 = Timebase interrupt pending
0 = Timebase interrupt not pending
TBR2:TBR0 — Timebase Rate Selection
These read/write bits are used to select the rate of timebase interrupts as shown in Table 21-1.
Table 21-1. Timebase Rate Selection for OSC1 = 32.768 kHz
TBR2
0
0
0
0
1
1
1
1
TBR1
0
0
1
1
0
0
1
1
TBR0
0
1
0
1
0
1
0
1
Divider
32,768
8192
2048
128
64
32
16
8
Timebase Interrupt Rate
Hz
ms
1
1000
4
250
16
62.5
256
~ 3.9
512
~2
1024
~1
2048
~0.5
4096
~0.24
NOTE
Do not change TBR2–TBR0 bits while the timebase is enabled (TBON = 1).
TACK— Timebase ACKnowledge
The TACK bit is a write-only bit and always reads as 0. Writing a 1 to this bit clears TBIF, the timebase
interrupt flag bit. Writing a 0 to this bit has no effect.
1 = Clear timebase interrupt flag
0 = No effect
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7
Freescale Semiconductor
227