MC68HC908GR8 Datasheet, PDF (189/286 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

SIM Bus Clock Control and Generation
Addr.
$FE04
$FE05
$FE06
Register Name
Bit 7
6
5
4
3
2
Read: IF6
IF5
IF4
IF3
IF2
IF1
Interrupt Status Register 1
(INT1)
Write:
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
Read: IF14
IF13
IF12
IF11
IF10
IF9
Interrupt Status Register 2
(INT2)
Write:
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
Read: 0
0
0
0
0
0
Interrupt Status Register 3
(INT3)
Write:
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
= Unimplemented
Figure 19-2. SIM I/O Register Summary (Continued)
1
Bit 0
0
0
R
R
0
0
IF8
IF7
R
R
0
0
IF16
IF15
R
R
0
0
19.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 19-3. This clock can
come from either an external oscillator or from the on-chip PLL. See Chapter 7 Clock Generator Module.
OSC2
OSC1
OSCILLATOR (OSC)
CGMXCLK
OSCSTOPENB
FROM
CONFIG
CGMRCLK
PHASE-LOCKED LOOP (PLL)
CGMOUT
TO TIMTB15A, ADC
SIM
SIM COUNTER
³2
BUS CLOCK
GENERATORS
SIMOSCEN
IT12
TO REST
OF CHIP
IT23
TO REST
OF CHIP
Figure 19-3. CGM Clock Signals
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7
Freescale Semiconductor
189