MC9S08DZ60CLH Datasheet, PDF (391/416 Pages) Freescale Semiconductor, Inc – MC9S08DZ60 Series Features

Appendix B
Timer Pulse-Width Modulator (TPMV2)
NOTE
This chapter refers to S08TPM version 2, which applies to the 3M05C and
older mask sets of this device. )M74K and newer mask set devices use
S08TPM version 3. If your device uses mask 0M74K or newer, please refer
to Chapter 16, “Timer Pulse-Width Modulator (S08TPMV3) for
information pertaining to that module.
The TPM uses one input/output (I/O) pin per channel, TPMxCHn where x is the TPM number (for
example, 1 or 2) and n is the channel number (for example, 0–4). The TPM shares its I/O pins with
general-purpose I/O port pins (refer to the Pins and Connections chapter for more information).
B.0.1 Features
The TPM has the following features:
• Each TPM may be configured for buffered, center-aligned pulse-width modulation (CPWM) on all
channels
• Clock sources independently selectable per TPM (multiple TPMs device)
• Selectable clock sources (device dependent): bus clock, fixed system clock, external pin
• Clock prescaler taps for divide by 1, 2, 4, 8, 16, 32, 64, or 128
• 16-bit free-running or up/down (CPWM) count operation
• 16-bit modulus register to control counter range
• Timer system enable
• One interrupt per channel plus a terminal count interrupt for each TPM module (multiple TPMs
device)
• Channel features:
— Each channel may be input capture, output compare, or buffered edge-aligned PWM
— Rising-edge, falling-edge, or any-edge input capture trigger
— Set, clear, or toggle output compare action
— Selectable polarity on PWM outputs
B.0.2 Block Diagram
Figure B-1 shows the structure of a TPM. Some MCUs include more than one TPM, with various numbers
of channels.
MC9S08DZ60 Series Data Sheet, Rev. 4
Freescale Semiconductor
391