MC9S08DZ60CLH Datasheet, PDF (180/416 Pages) Freescale Semiconductor, Inc – MC9S08DZ60 Series Features

Chapter 10 Analog-to-Digital Converter (S08ADC12V1)
7
6
5
4
R COCO
W
AIEN
ADCO
3
2
1
0
ADCH
Reset:
0
0
0
1
1
1
1
1
Figure 10-3. Status and Control Register (ADCSC1)
Table 10-3. ADCSC1 Field Descriptions
Field
7
COCO
6
AIEN
5
ADCO
4:0
ADCH
Description
Conversion Complete Flag. The COCO flag is a read-only bit set each time a conversion is completed when the
compare function is disabled (ACFE = 0). When the compare function is enabled (ACFE = 1), the COCO flag is
set upon completion of a conversion only if the compare result is true. This bit is cleared when ADCSC1 is written
or when ADCRL is read.
0 Conversion not completed
1 Conversion completed
Interrupt Enable AIEN enables conversion complete interrupts. When COCO becomes set while AIEN is high,
an interrupt is asserted.
0 Conversion complete interrupt disabled
1 Conversion complete interrupt enabled
Continuous Conversion Enable. ADCO enables continuous conversions.
0 One conversion following a write to the ADCSC1 when software triggered operation is selected, or one
conversion following assertion of ADHWT when hardware triggered operation is selected.
1 Continuous conversions initiated following a write to ADCSC1 when software triggered operation is selected.
Continuous conversions are initiated by an ADHWT event when hardware triggered operation is selected.
Input Channel Select. The ADCH bits form a 5-bit field that selects one of the input channels. The input channels
are detailed in Table 10-4.
The successive approximation converter subsystem is turned off when the channel select bits are all set. This
feature allows for explicit disabling of the ADC and isolation of the input channel from all sources. Terminating
continuous conversions this way prevents an additional, single conversion from being performed. It is not
necessary to set the channel select bits to all ones to place the ADC in a low-power state when continuous
conversions are not enabled because the module automatically enters a low-power state when a conversion
completes.
Table 10-4. Input Channel Select
ADCH
00000–01111
10000–11011
11100
11101
11110
11111
Input Select
AD0–15
AD16–27
Reserved
V_REFH
V_REFL
Module disabled
MC9S08DZ60 Series Data Sheet, Rev. 4
180
Freescale Semiconductor