MC9S08DZ60CLH Datasheet, PDF (152/416 Pages) Freescale Semiconductor, Inc – MC9S08DZ60 Series Features

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1)
8.4.7 Fixed Frequency Clock
The MCG presents the divided reference clock as MCGFFCLK for use as an additional clock source. The
MCGFFCLK frequency must be no more than 1/4 of the MCGOUT frequency to be valid. Because of this
requirement, the MCGFFCLK is not valid in bypass modes for the following combinations of BDIV and
RDIV values:
• BDIV=00 (divide by 1), RDIV < 010
• BDIV=01 (divide by 2), RDIV < 011
When MCGFFCLK is valid then MCGFFCLKVALID is set to 1. When MCGFFCLK is not valid then
MCGFFCLKVALID is set to 0.
8.5 Initialization / Application Information
This section describes how to initialize and configure the MCG module in application. The following
sections include examples on how to initialize the MCG and properly switch between the various available
modes.
8.5.1 MCG Module Initialization Sequence
The MCG comes out of reset configured for FEI mode with the BDIV set for divide-by-2. The internal
reference will stabilize in t_irefst microseconds before the FLL can acquire lock. As soon as the internal
reference is stable, the FLL will acquire lock in t_{fll_lock} milliseconds.
Upon POR, the internal reference will require trimming to guarantee an accurate clock. Freescale
recommends using FLASH location 0xFFAE for storing the fine trim bit, FTRIM in the MCGSC register,
and 0xFFAF for storing the 8-bit trim value in the MCGTRM register. The MCU will not automatically
copy the values in these FLASH locations to the respective registers. Therefore, user code must copy these
values from FLASH to the registers.
NOTE
The BDIV value should not be changed to divide-by-1 without first
trimming the internal reference. Failure to do so could result in the MCU
running out of specification.
8.5.1.1 Initializing the MCG
Because the MCG comes out of reset in FEI mode, the only MCG modes which can be directly switched
to upon reset are FEE, FBE, and FBI modes (see Figure 8-8). Reaching any of the other modes requires
first configuring the MCG for one of these three initial modes. Care must be taken to check relevant status
bits in the MCGSC register reflecting all configuration changes within each mode.
To change from FEI mode to FEE or FBE modes, follow this procedure:
1. Enable the external clock source by setting the appropriate bits in MCGC2.
2. Write to MCGC1 to select the clock mode.
MC9S08DZ60 Series Data Sheet, Rev. 4
152
Freescale Semiconductor