MC9S08DZ60CLH Datasheet, PDF (146/416 Pages) Freescale Semiconductor, Inc – MC9S08DZ60 Series Features

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1)
8.4 Functional Description
8.4.1 Operational Modes
IREFS=1
CLKS=00
PLLS=0
FLL Engaged
Internal (FEI)
IREFS=1
CLKS=01
PLLS=0
BDM Enabled
or LP=0
FLL Bypassed
Internal (FBI)
IREFS=1
CLKS=01
PLLS=0
BDM Disabled
and LP=1
Bypassed
Low Power
Internal (BLPI)
FLL Engaged
External (FEE)
IREFS=0
CLKS=00
PLLS=0
FLL Bypassed
External (FBE)
IREFS=0
CLKS=10
PLLS=0
BDM Enabled
or LP=0
PLL Bypassed
External (PBE)
Bypassed
Low Power
External (BLPE)
IREFS=0
CLKS=10
BDM Disabled
and LP=1
IREFS=0
CLKS=10
PLLS=1
BDM Enabled
or LP=0
PLL Engaged IREFS=0
External (PEE) CLKS=00
PLLS=1
Entered from any state
when MCU enters stop
Stop
Returns to state that was active
before MCU entered stop, unless
RESET occurs while in stop.
Figure 8-8. Clock Switching Modes
MC9S08DZ60 Series Data Sheet, Rev. 4
146
Freescale Semiconductor