MC9S08DZ60CLH Datasheet, PDF (182/416 Pages) Freescale Semiconductor, Inc – MC9S08DZ60 Series Features

Chapter 10 Analog-to-Digital Converter (S08ADC12V1)
If the MODE bits are changed, any data in ADCRH becomes invalid.
7
R
0
W
Reset:
0
6
5
4
3
2
1
0
0
0
0
ADR11
ADR10
ADR9
ADR8
0
0
0
0
0
0
0
Figure 10-5. Data Result High Register (ADCRH)
10.3.4 Data Result Low Register (ADCRL)
ADCRL contains the lower eight bits of the result of a 12-bit or 10-bit conversion, and all eight bits of an
8-bit conversion. This register is updated each time a conversion completes except when automatic
compare is enabled and the compare condition is not met. When a compare event does occur, the value is
the addition of the conversion result and the two’s complement of the compare value. In 12-bit and 10-bit
mode, reading ADCRH prevents the ADC from transferring subsequent conversion results into the result
registers until ADCRL is read. If ADCRL is not read until the after next conversion is completed, the
intermediate conversion results are lost. In 8-bit mode, there is no interlocking with ADCRH. If the MODE
bits are changed, any data in ADCRL becomes invalid.
R
W
Reset:
7
ADR7
0
6
ADR6
5
ADR5
4
ADR4
3
ADR3
2
ADR2
0
0
0
0
0
Figure 10-6. Data Result Low Register (ADCRL)
1
ADR1
0
0
ADR0
0
10.3.5 Compare Value High Register (ADCCVH)
In 12-bit mode, the ADCCVH register holds the upper four bits of the 12-bit compare value. When the
compare function is enabled, these bits are compared to the upper four bits of the result following a
conversion in 12-bit mode.
7
R
0
W
Reset:
0
6
5
4
3
2
1
0
0
0
0
ADCV11 ADCV10 ADCV9 ADCV8
0
0
0
0
0
0
0
Figure 10-7. Compare Value High Register (ADCCVH)
MC9S08DZ60 Series Data Sheet, Rev. 4
182
Freescale Semiconductor