MC9S08DZ60CLH Datasheet, PDF (277/416 Pages) Freescale Semiconductor, Inc – MC9S08DZ60 Series Features

SPE
ENABLE
SPI SYSTEM
LSBFE
Tx BUFFER (WRITE SPID)
SHIFT
OUT
SPI SHIFT REGISTER
SHIFT
IN
Rx BUFFER (READ SPID)
SHIFT
DIRECTION
SHIFT Rx BUFFER Tx BUFFER
CLOCK
FULL
EMPTY
Chapter 13 Serial Peripheral Interface (S08SPIV3)
PIN CONTROL
M
S
MOSI
(MOMI)
M
S
SPC0
BIDIROE
MISO
(SISO)
BUS RATE
CLOCK
SPIBR
CLOCK GENERATOR
MSTR
MASTER/SLAVE
MODE SELECT
CLOCK
LOGIC
MODE FAULT
DETECTION
MASTER CLOCK
SLAVE CLOCK
MODFEN
SSOE
M
S
MASTER/
SLAVE
SPSCK
SS
SPRF
SPTEF
SPTIE
MODF
SPIE
Figure 13-3. SPI Module Block Diagram
SPI
INTERRUPT
REQUEST
13.1.3 SPI Baud Rate Generation
As shown in Figure 13-4, the clock source for the SPI baud rate generator is the bus clock. The three
prescale bits (SPPR2:SPPR1:SPPR0) choose a prescale divisor of 1, 2, 3, 4, 5, 6, 7, or 8. The three rate
select bits (SPR2:SPR1:SPR0) divide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, or 256
to get the internal SPI master mode bit-rate clock.
MC9S08DZ60 Series Data Sheet, Rev. 4
Freescale Semiconductor
277