MC9S08DZ60CLH Datasheet, PDF (142/416 Pages) Freescale Semiconductor, Inc – MC9S08DZ60 Series Features

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1)
8.3.3 MCG Trim Register (MCGTRM)
7
R
W
POR:
1
Reset:
U
6
5
4
3
TRIM
2
1
0
0
0
0
0
0
0
0
U
U
U
U
U
U
U
Figure 8-5. MCG Trim Register (MCGTRM)
Table 8-3. MCG Trim Register Field Descriptions
Field
7:0
TRIM
Description
MCG Trim Setting — Controls the internal reference clock frequency by controlling the internal reference clock
period. The TRIM bits are binary weighted (i.e., bit 1 will adjust twice as much as bit 0). Increasing the binary
value in TRIM will increase the period, and decreasing the value will decrease the period.
An additional fine trim bit is available in MCGSC as the FTRIM bit.
If a TRIM[7:0] value stored in nonvolatile memory is to be used, it’s the user’s responsibility to copy that value
from the nonvolatile memory location to this register.
MC9S08DZ60 Series Data Sheet, Rev. 4
142
Freescale Semiconductor