MC9S08DZ60CLH Datasheet, PDF (229/416 Pages) Freescale Semiconductor, Inc – MC9S08DZ60 Series Features

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
Table 12-7. Time Segment 2 Values
TSEG22
TSEG21
TSEG20
Time Segment 2
0
0
0
1 Tq clock cycle¹
0
0
1
2 Tq clock cycles
:
:
:
:
1
1
0
7 Tq clock cycles
1
1
1
8 Tq clock cycles
1 _{This setting is not valid. Please refer to Table 12-35 for valid settings.}
Table 12-8. Time Segment 1 Values
TSEG13
TSEG12
TSEG11
TSEG10
Time segment 1
0
0
0
0
1 Tq clock cycle¹
0
0
0
1
2 Tq clock cycles¹
0
0
1
0
3 Tq clock cycles¹
0
0
1
1
4 Tq clock cycles
:
:
:
:
:
1
1
1
0
15 Tq clock cycles
1
1
1
1
16 Tq clock cycles
1 _{This setting is not valid. Please refer to Table 12-35 for valid settings.}
The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time
quanta (Tq) clock cycles per bit (as shown in Table 12-7 and Table 12-8).
Eqn. 12-1
Bit Time= ⁽---P----r---e---f-s-C--c---A-a----Nl--e--C-r----L--v--K-a----l--u----e----⁾ • (1 + TimeSegment1 + TimeSegment2)
12.3.4.1 MSCAN Receiver Flag Register (CANRFLG)
A flag can be cleared only by software (writing a 1 to the corresponding bit position) when the condition
which caused the setting is no longer valid. Every flag has an associated interrupt enable bit in the
CANRIER register.
7
R
WUPIF
W
6
CSCIF
5
RSTAT1
4
RSTAT0
3
TSTAT1
2
TSTAT0
1
OVRIF
0
RXF
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-8. MSCAN Receiver Flag Register (CANRFLG)
MC9S08DZ60 Series Data Sheet, Rev. 4
Freescale Semiconductor
229