MC9S08DZ60CLH Datasheet, PDF (190/416 Pages) Freescale Semiconductor, Inc – MC9S08DZ60 Series Features

Chapter 10 Analog-to-Digital Converter (S08ADC12V1)
When a conversion is aborted, the contents of the data registers, ADCRH and ADCRL, are not altered.
However, they continue to be the values transferred after the completion of the last successful conversion.
If the conversion was aborted by a reset, ADCRH and ADCRL return to their reset states.
10.4.4.4 Power Control
The ADC module remains in its idle state until a conversion is initiated. If ADACK is selected as the
conversion clock source, the ADACK clock generator is also enabled.
Power consumption when active can be reduced by setting ADLPC. This results in a lower maximum value
for f_ADCK (see the electrical specifications).
10.4.4.5 Sample Time and Total Conversion Time
The total conversion time depends on the sample time (as determined by ADLSMP), the MCU bus
frequency, the conversion mode (8-bit, 10-bit or 12-bit), and the frequency of the conversion clock (f_ADCK).
After the module becomes active, sampling of the input begins. ADLSMP selects between short (3.5
ADCK cycles) and long (23.5 ADCK cycles) sample times.When sampling is complete, the converter is
isolated from the input channel and a successive approximation algorithm is performed to determine the
digital value of the analog signal. The result of the conversion is transferred to ADCRH and ADCRL upon
completion of the conversion algorithm.
If the bus frequency is less than the f_ADCK frequency, precise sample time for continuous conversions
cannot be guaranteed when short sample is enabled (ADLSMP=0). If the bus frequency is less than 1/11th
of the f_ADCK frequency, precise sample time for continuous conversions cannot be guaranteed when long
sample is enabled (ADLSMP=1).
The maximum total conversion time for different conditions is summarized in Table 10-13.
Table 10-13. Total Conversion Time vs. Control Conditions
Conversion Type
Single or first continuous 8-bit
Single or first continuous 10-bit or 12-bit
Single or first continuous 8-bit
Single or first continuous 10-bit or 12-bit
Single or first continuous 8-bit
Single or first continuous 10-bit or 12-bit
Single or first continuous 8-bit
Single or first continuous 10-bit or 12-bit
Subsequent continuous 8-bit;
f_BUS > f_ADCK
Subsequent continuous 10-bit or 12-bit;
f_BUS > f_ADCK
Subsequent continuous 8-bit;
f_BUS > f_ADCK/11
ADICLK
0x, 10
0x, 10
0x, 10
0x, 10
11
11
11
11
xx
xx
xx
ADLSMP
0
0
1
1
0
0
1
1
0
0
1
Max Total Conversion Time
20 ADCK cycles + 5 bus clock cycles
23 ADCK cycles + 5 bus clock cycles
40 ADCK cycles + 5 bus clock cycles
43 ADCK cycles + 5 bus clock cycles
5 μs + 20 ADCK + 5 bus clock cycles
5 μs + 23 ADCK + 5 bus clock cycles
5 μs + 40 ADCK + 5 bus clock cycles
5 μs + 43 ADCK + 5 bus clock cycles
17 ADCK cycles
20 ADCK cycles
37 ADCK cycles
MC9S08DZ60 Series Data Sheet, Rev. 4
190
Freescale Semiconductor