MC9S08DZ60CLH Datasheet, PDF (111/416 Pages) Freescale Semiconductor, Inc – MC9S08DZ60 Series Features

6.5.7 Port G Registers
Port G is controlled by the registers listed below.
6.5.7.1 Port G Data Register (PTGD)
Chapter 6 Parallel Input/Output Control
7
R
0
W
6
5
4
3
2
1
0
0
PTGD5
PTGD4
PTGD3
PTGD2
PTGD1
PTGD0
Reset:
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-42. Port G Data Register (PTGD)
Table 6-40. PTGD Register Field Descriptions
Field
Description
5:0
PTGD[5:0]
Port G Data Register Bits — For port G pins that are inputs, reads return the logic level on the pin. For port G
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port G pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTGD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pull-ups disabled.
6.5.7.2 Port G Data Direction Register (PTGDD)
7
R
0
W
6
5
4
3
2
1
0
0
PTGDD5 PTGDD4 PTGDD3 PTGDD2 PTGDD1 PTGDD0
Reset:
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-43. Port G Data Direction Register (PTGDD)
Table 6-41. PTGDD Register Field Descriptions
Field
Description
5:0
Data Direction for Port G Bits — These read/write bits control the direction of port G pins and what is read for
PTGDD[5:0] PTGD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port G bit n and PTGD reads return the contents of PTGDn.
MC9S08DZ60 Series Data Sheet, Rev. 4
Freescale Semiconductor
111