MC9S08DZ60CLH Datasheet, PDF (141/416 Pages) Freescale Semiconductor, Inc – MC9S08DZ60 Series Features

8.3.2
Chapter 8 Multi-Purpose Clock Generator (S08MCGV1)
MCG Control Register 2 (MCGC2)
R
W
Reset:
7
6
BDIV
5
RANGE
4
HGO
3
2
1
0
LP
EREFS ERCLKEN EREFSTEN
0
1
0
0
0
0
0
0
Figure 8-4. MCG Control Register 2 (MCGC2)
Table 8-2. MCG Control Register 2 Field Descriptions
Field
Description
7:6
BDIV
Bus Frequency Divider — Selects the amount to divide down the clock source selected by the CLKS bits in the
MCGC1 register. This controls the bus frequency.
00 Encoding 0 — Divides selected clock by 1
01 Encoding 1 — Divides selected clock by 2 (reset default)
10 Encoding 2 — Divides selected clock by 4
11 Encoding 3 — Divides selected clock by 8
5
RANGE
Frequency Range Select — Selects the frequency range for the external oscillator or external clock source.
1 High frequency range selected for the external oscillator of 1 MHz to 16 MHz (1 MHz to 40 MHz for external
clock source)
0 Low frequency range selected for the external oscillator of 32 kHz to 100 kHz (32 kHz to 1 MHz for external
clock source)
4
HGO
High Gain Oscillator Select — Controls the external oscillator mode of operation.
1 Configure external oscillator for high gain operation
0 Configure external oscillator for low power operation
3
Low Power Select — Controls whether the FLL (or PLL) is disabled in bypassed modes.
LP
1 FLL (or PLL) is disabled in bypass modes (lower power).
0 FLL (or PLL) is not disabled in bypass modes.
2
EREFS
External Reference Select — Selects the source for the external reference clock.
1 Oscillator requested
0 External Clock Source requested
1
External Reference Enable — Enables the external reference clock for use as MCGERCLK.
ERCLKEN 1 MCGERCLK active
0 MCGERCLK inactive
0
External Reference Stop Enable — Controls whether or not the external reference clock remains enabled when
EREFSTEN the MCG enters stop mode.
1 External reference clock stays enabled in stop if ERCLKEN is set or if MCG is in FEE, FBE, PEE, PBE, or
BLPE mode before entering stop
0 External reference clock is disabled in stop
MC9S08DZ60 Series Data Sheet, Rev. 4
Freescale Semiconductor
141