MC9S08DZ60CLH Datasheet, PDF (228/416 Pages) Freescale Semiconductor, Inc – MC9S08DZ60 Series Features

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
Table 12-5. Baud Rate Prescaler
BRP5
0
0
0
0
:
1
BRP4
0
0
0
0
:
1
BRP3
0
0
0
0
:
1
BRP2
0
0
0
0
:
1
BRP1
0
0
1
1
:
1
BRP0
0
1
0
1
:
1
Prescaler value (P)
1
2
3
4
:
64
12.3.4 MSCAN Bus Timing Register 1 (CANBTR1)
The CANBTR1 register configures various CAN bus timing parameters of the MSCAN module.
R
W
Reset:
7
SAMP
0
6
TSEG22
5
TSEG21
4
TSEG20
3
TSEG13
2
TSEG12
0
0
0
0
0
Figure 12-7. MSCAN Bus Timing Register 1 (CANBTR1)
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Table 12-6. CANBTR1 Register Field Descriptions
1
TSEG11
0
0
TSEG10
0
Field
Description
7
SAMP
Sampling — This bit determines the number of CAN bus samples taken per bit time.
0 One sample per bit.
1 Three samples per bit¹.
If SAMP = 0, the resulting bit value is equal to the value of the single bit positioned at the sample point. If
SAMP = 1, the resulting bit value is determined by using majority rule on the three total samples. For higher bit
rates, it is recommended that only one sample is taken per bit time (SAMP = 0).
6:4
Time Segment 2 — Time segments within the bit time fix the number of clock cycles per bit time and the location
TSEG2[2:0] of the sample point (see Figure 12-43). Time segment 2 (TSEG2) values are programmable as shown in
Table 12-7.
3:0
Time Segment 1 — Time segments within the bit time fix the number of clock cycles per bit time and the location
TSEG1[3:0] of the sample point (see Figure 12-43). Time segment 1 (TSEG1) values are programmable as shown in
Table 12-8.
1 _{In this case, PHASE_SEG1 must be at least 2 time quanta (Tq).}
MC9S08DZ60 Series Data Sheet, Rev. 4
228
Freescale Semiconductor