MC9S08DZ60CLH Datasheet, PDF (260/416 Pages) Freescale Semiconductor, Inc – MC9S08DZ60 Series Features

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
If the bus clock is generated from a PLL, it is recommended to select the oscillator clock rather than the
bus clock due to jitter considerations, especially at the faster CAN bus rates. PLL lock may also be too
wide to ensure adequate clock tolerance.
For microcontrollers without a clock and reset generator (CRG), CANCLK is driven from the crystal
oscillator (oscillator clock).
A programmable prescaler generates the time quanta (Tq) clock from CANCLK. A time quantum is the
atomic unit of time handled by the MSCAN.
Tq= ^-₍^{--P----r---e----s-f--c-C---aA----lN--e--C-r---L---v-K--a----l--u----e----}₎
Eqn. 12-2
A bit time is subdivided into three segments as described in the Bosch CAN specification. (see
Figure 12-43):
• SYNC_SEG: This segment has a fixed length of one time quantum. Signal edges are expected to
happen within this section.
• Time Segment 1: This segment includes the PROP_SEG and the PHASE_SEG1 of the CAN
standard. It can be programmed by setting the parameter TSEG1 to consist of 4 to 16 time quanta.
• Time Segment 2: This segment represents the PHASE_SEG2 of the CAN standard. It can be
programmed by setting the TSEG2 parameter to be 2 to 8 time quanta long.
Bit Rate= ₍---n----u----m------b----e---r------o----f---f--T^T---^q-i--m-----e-------Q-----u----a----n----t--a----₎
Eqn. 12-3
NRZ Signal
SYNC_SEG
Time Segment 1
(PROP_SEG + PHASE_SEG1)
Time Segment 2
(PHASE_SEG2)
1
4 ... 16
8 ... 25 Time Quanta
= 1 Bit Time
2 ... 8
Transmit Point
Sample Point
(single or triple sampling)
Figure 12-43. Segments within the Bit Time
MC9S08DZ60 Series Data Sheet, Rev. 4
260
Freescale Semiconductor