MC9S08DZ60CLH Datasheet, PDF (238/416 Pages) Freescale Semiconductor, Inc – MC9S08DZ60 Series Features

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
7
6
5
4
3
2
1
R
0
0
0
0
0
0
0
W
Reset:
0
0
0
0
0
0
0
= Unimplemented
Figure 12-16. MSCAN Miscellaneous Register (CANMISC)
0
BOHOLD
0
Read: Anytime
Write: Anytime; write of ‘1’ clears flag; write of ‘0’ ignored
Table 12-19. CANMISC Register Field Descriptions
Field
Description
0
BOHOLD
Bus-off State Hold Until User Request — If BORM is set in Section 12.3.2, “MSCAN Control Register 1
(CANCTL1), this bit indicates whether the module has entered the bus-off state. Clearing this bit requests the
recovery from bus-off. Refer to Section 12.6.2, “Bus-Off Recovery,” for details.
0 Module is not bus-off or recovery has been requested by user in bus-off state
1 Module is bus-off and holds this state until user request
12.3.13 MSCAN Receive Error Counter (CANRXERR)
This register reflects the status of the MSCAN receive error counter.
7
R RXERR7
W
Reset:
0
6
RXERR6
5
RXERR5
0
0
= Unimplemented
4
RXERR4
0
3
RXERR3
0
2
RXERR2
0
1
RXERR1
0
0
RXERR0
0
Figure 12-17. MSCAN Receive Error Counter (CANRXERR)
Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and
INITAK = 1)
Write: Unimplemented
NOTE
Reading this register when in any other mode other than sleep or
initialization mode may return an incorrect value. For MCUs with dual
CPUs, this may result in a CPU fault condition.
Writing to this register when in special modes can alter the MSCAN
functionality.
MC9S08DZ60 Series Data Sheet, Rev. 4
238
Freescale Semiconductor