MC9S08DZ60CLH Datasheet, PDF (250/416 Pages) Freescale Semiconductor, Inc – MC9S08DZ60 Series Features

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
Section 12.3.1, “MSCAN Control Register 0 (CANCTL0)”). In case of a transmission, the CPU can only
read the time stamp after the respective transmit buffer has been flagged empty.
The timer value, which is used for stamping, is taken from a free running internal CAN bit clock. A timer
overrun is not indicated by the MSCAN. The timer is reset (all bits set to 0) during initialization mode. The
CPU can only read the time stamp registers.
R
W
Reset:
7
TSR15
x
6
TSR14
5
TSR13
4
TSR12
3
TSR11
2
TSR10
x
x
x
x
x
Figure 12-36. Time Stamp Register — High Byte (TSRH)
1
TSR9
x
0
TSR8
x
R
W
Reset:
7
TSR7
x
6
TSR6
5
TSR5
4
TSR4
3
TSR3
2
TSR2
x
x
x
x
x
Figure 12-37. Time Stamp Register — Low Byte (TSRL)
1
TSR1
x
0
TSR0
x
Read: Anytime when TXEx flag is set (see Section 12.3.6, “MSCAN Transmitter Flag Register
(CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 12.3.10,
“MSCAN Transmit Buffer Selection Register (CANTBSEL)”).
Write: Unimplemented
12.5 Functional Description
12.5.1 General
This section provides a complete functional description of the MSCAN. It describes each of the features
and modes listed in the introduction.
MC9S08DZ60 Series Data Sheet, Rev. 4
250
Freescale Semiconductor