MC9S08DZ60CLH Datasheet, PDF (383/416 Pages) Freescale Semiconductor, Inc – MC9S08DZ60 Series Features

Appendix A Electrical Characteristics
A.12 AC Characteristics
This section describes ac timing characteristics for each peripheral system.
A.12.1 Control Timing
Table A-13. Control Timing
Nu
m
C
Rating
Symbol
Min
Typical¹ Max Unit
1
D/
P
Bus frequency (t_cyc = 1/f_Bus)
f_Bus
dc
—
20
MHz
2 T Internal low-power oscillator period
t_LPO
—
1500
—
μs
3
D _{External reset pulse width}²
t_extrst
1.5 x t_cyc
—
ns
4
D _{Reset low drive}³
t_rstdrv
34 x t_cyc
—
ns
5 D Active background debug mode latch setup time
t_MSSU
25
—
ns
6 D Active background debug mode latch hold time
t_MSH
25
—
ns
IRQ/PIAx/ PIBx/PIDx pulse width
7
D
Asynchronous path²
Synchronous path³
t_ILIH, t_IHIL
100
—
1.5 t_cyc
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)⁴
Slew rate control disabled (PTxSE = 0)
t_Rise, t_Fall
—
40
Slew rate control enabled (PTxSE = 1)
8T
Port rise and fall time —
—
75
High output drive (PTxDS = 1) (load = 50 pF)⁴
Slew rate control disabled (PTxSE = 0)
t_Rise, t_Fall
—
11
Slew rate control enabled (PTxSE = 1)
—
35
—
ns
ns
ns
1 _{Typical data was characterized at 5.0 V, 25°C unless otherwise stated.}
2 _{This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to}
override reset requests from internal sources.
3 _{When any reset is initiated, internal circuitry drives the RESET pin low for about 34 cycles of tcyc. After POR reset, the bus}
clock frequency changes to the untrimmed DCO frequency (freset = (f_{dco_ut})/4) because TRIM is reset to 0x80 and FTRIM is
reset to 0; and there is an extra divide-by-two because BDIV is reset to 0:1. After other resets, trim stays at the pre-reset value.
4 _{Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40°C to 125°C.}
RESET PIN
t_extrst
Figure A-2. Reset Timing
MC9S08DZ60 Series Data Sheet, Rev. 4
Freescale Semiconductor
383