MC9S08DZ60CLH Datasheet, PDF (124/416 Pages) Freescale Semiconductor, Inc – MC9S08DZ60 Series Features

Chapter 7 Central Processor Unit (S08CPUV3)
7.5 HCS08 Instruction Set Summary
Table 7-2 provides a summary of the HCS08 instruction set in all possible addressing modes. The table
shows operand construction, execution time in internal bus clock cycles, and cycle-by-cycle details for
each addressing mode variation of each instruction.
Source
Form
ADC #opr8i
ADC opr8a
ADC opr16a
ADC oprx16,X
ADC oprx8,X
ADC ,X
ADC oprx16,SP
ADC oprx8,SP
ADD #opr8i
ADD opr8a
ADD opr16a
ADD oprx16,X
ADD oprx8,X
ADD ,X
ADD oprx16,SP
ADD oprx8,SP
AIS #opr8i
AIX #opr8i
AND #opr8i
AND opr8a
AND opr16a
AND oprx16,X
AND oprx8,X
AND ,X
AND oprx16,SP
AND oprx8,SP
ASL opr8a
ASLA
ASLX
ASL oprx8,X
ASL ,X
ASL oprx8,SP
ASR opr8a
ASRA
ASRX
ASR oprx8,X
ASR ,X
ASR oprx8,SP
Table 7-2. Instruction Set Summary (Sheet 1 of 9)
Operation
Add with Carry
A ← (A) + (M) + (C)
Add without Carry
A ← (A) + (M)
Add Immediate Value (Signed) to
Stack Pointer
SP ← (SP) + (M)
Add Immediate Value (Signed) to
Index Register (H:X)
H:X ← (H:X) + (M)
Logical AND
A ← (A) & (M)
Arithmetic Shift Left
C
b7
(Same as LSL)
0
b0
Arithmetic Shift Right
C
b7
b0
Object Code
Cyc-by-Cyc
Details
Affect
on CCR
V11H INZC
IMM
A9 ii
2 pp
DIR
B9 dd
3 rpp
EXT
C9 hh ll 4 prpp
IX2
D9 ee ff 4 prpp
IX1
E9 ff
3 rpp
IX
F9
3 rfp
SP2
9E D9 ee ff 5 pprpp
SP1
9E E9 ff
4 prpp
↕11↕ –↕↕↕
IMM
AB ii
2 pp
DIR
BB dd
3 rpp
EXT
CB hh ll 4 prpp
IX2
DB ee ff 4 prpp
IX1
EB ff
3 rpp
IX
FB
3 rfp
SP2
9E DB ee ff 5 pprpp
SP1
9E EB ff
4 prpp
↕11↕ –↕↕↕
IMM
A7 ii
2 pp
–11– ––––
IMM
AF ii
2 pp
IMM
A4 ii
2 pp
DIR
B4 dd
3 rpp
EXT
C4 hh ll 4 prpp
IX2
D4 ee ff 4 prpp
IX1
E4 ff
3 rpp
IX
F4
3 rfp
SP2
9E D4 ee ff 5 pprpp
SP1
9E E4 ff
4 prpp
DIR
38 dd
5 rfwpp
INH
48
1p
INH
58
1p
IX1
68 ff
5 rfwpp
IX
78
4 rfwp
SP1
9E 68 ff
6 prfwpp
DIR
37 dd
5 rfwpp
INH
47
1p
INH
57
1p
IX1
67 ff
5 rfwpp
IX
77
4 rfwp
SP1
9E 67 ff
6 prfwpp
–11– ––––
011– –↕↕–
↕11– –↕↕↕
↕11– –↕↕↕
MC9S08DZ60 Series Data Sheet, Rev. 4
124
Freescale Semiconductor