DS80CH11 Datasheet, PDF (86/88 Pages) Dallas Semiconductor – System Energy Manager

DS80CH11
13.6 2–WIRE AC TIMING CHARACTERISTICS
PARAMETER
SYMBOL
START Condition Hold Time
SCLx Low Time
SCLx High Time
SCLx, SDAx Rise Time
SCLx, SDAx Fall Time
Data Setup Time
Data Hold Time
Repeated START Setup Time
Repeated STOP Setup Time
Bus Free Time
t_STAH
t_SCL
t_SCH
t_SR
t_SF
t_2DS
t_2DH
t_RSTA
t_RSTO
t_2BF
INPUT
> 14 t_CLK (4)
> 16 t_CLK (4)
> 14 t_CLK (4)
< 300 ns⁽¹⁾
< 300 ns⁽³⁾
> 100 ns
> 0 ns
> 14 t_CLK (4)
> 14 t_CLK (4)
> 14 t_CLK (4)
(0°C to 70°C; V_CC=5.0 ± 10%)
OUTPUT
> 1.0 µs⁽¹⁾
> 1.3 µs⁽¹⁾
> 0.6 µs⁽¹⁾
– ⁽²⁾
< 300 ns
> 250 ns⁽¹⁾
> 8 t_CLK – t_SF (4)
> 600 ns⁽¹⁾
> 600 ns⁽¹⁾
> 1.3 µs⁽¹⁾
NOTES:
1. At 400Kbps. For other bit rates this value is multiplied by 400 / f_2W.
2. Determined by the external bus line capacitance and the external bus line pull–up resistor; this must be < 300 ns
@ 400Kbps.
3. Spikes on the SDAx and SCLx lines with a duration of less than 50 ns will be filtered out. Maximum capacitance
on either SDAx and SCLx = 400 pF.
4. Where t_CLK is the period of the XTAL oscillator and the instruction cycle rate is set to 4 clocks (default). The fre-
quency of the XTAL oscillator should be greater than 5 MHz for 400Kbps operation.
5. Both 2–Wire ports are identical and therefore only SDAx and SCLx are used here to simplify all notations.
SDAx = SDA1 or SDA2 and SCLx = SCL1 or SCL2 (“x” = 1 or 2).
2–WIRE SERIAL I/O TIMING Figure 13–12
t_SF
t_SR
SDAx
t_STAH
SCLx
t_2DS
t_SR
t_SF
t_2DH
t_SCL
t_SCH
t_RSTO
t_RSTA
t_2DS
t_2DS
t_2BF
011200 86/88