DS80CH11 Datasheet, PDF (24/88 Pages) Dallas Semiconductor – System Energy Manager

DS80CH11
4.0 MEMORY RESOURCES
4.1 OVERVIEW
The SEM contains the following memory resources and
features:
SRAM is between 0000h and 00FFh. Any MOVX
instruction that uses this area will go to the on–chip RAM
while enabled. MOVX addresses greater than 256
automatically go to external memory through Ports
0 & 2.
• 256 bytes of on–chip direct (scratchpad) RAM
• 256 bytes of on–chip MOVX data RAM
• Off–chip program and data memory expansion
• Software enable/disable of on–chip data memory
4.2 DATA MEMORY ACCESS
Unlike many 8051 derivatives, the SEM contains on–
chip data memory. Although physically on–chip, soft-
ware accesses this area in the same way off–chip data
memory is accessed: via the MOVX instruction. The
256 bytes of SRAM is located between address 0000h
and 00FFh.
Access to the on–chip data RAM is optional under soft-
ware control. When enabled by software, the data
DATA MEMORY ACCESS CONTROL Table 4–1
DME1 DME0
DATA MEMORY ADDRESS
0
0
0
1
1
0
1
1
0000h – FFFFh
0000h – 00FFh
0100h – FFFFh
Reserved
0000h – 00FFh
0100h – FFFBh
FFFCh
FFFDh – FFFFh
When disabled, the 256 bytes of memory area is trans-
parent to the system memory map. Any MOVX directed
to the space between 0000h and FFFFh goes to the
expanded bus on Ports 0 & 2. This also is the default
condition. This default allows the SEM to drop into an
existing system that uses these addresses for other
hardware and still have full compatibility.
The on–chip data area is selected by software using two
bits in the Power Management Register at location C4h.
This selection is dynamically programmable. Thus
access to the on–chip area becomes transparent to
reach off–chip devices at the same addresses. The
control bits are DME1 (PMR.1) and DME0 (PMR.0).
Their operation is described in Table 4–1.
MEMORY FUNCTION
External Data Memory (Default condition)
Internal SRAM Data Memory
External Data Memory
Reserved
Internal SRAM Data Memory
Reserved – no external access
Read access to the status of lock bits
Reserved – no external access
Notes on the status byte read at FFFCh with DME1, 0 = 1, 1: Bits 2–0 reflect the programmed status of the security
lock bits LB3–LB1. They are individually set to a logic 1 to correspond to a security lock bit that has been programmed.
These status bits allow software to verify that the part has been locked before running if desired. The bits are read
only.
4.2.1 Stretch Memory Cycle
The SEM allows software to adjust the speed of off–chip
data memory access. The micro is capable of perform-
ing the MOVX in as little as two instruction cycles. The
on–chip SRAM uses this speed and any MOVX instruc-
tion directed internally uses two cycles. However, the
time can be stretched for interface to external devices.
This allows access to both fast memory and slow
memory or peripherals with no glue logic. Even in high–
speed systems, it may not be necessary or desirable to
perform off–chip data memory access at full speed. In
addition, there are a variety of memory mapped periph-
erals such as LCDs or UARTs that are slow.
Operation of the Stretch MOVX function is fully docu-
mented in the Dallas High Speed Micro User’s Guide.
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