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DS80CH11 Datasheet, PDF (30/88 Pages) Dallas Semiconductor – System Energy Manager
DS80CH11
5.0 CORE I/O RESOURCES
The SEM incorporates a full complement of the
80C52–compatible I/O resources as well as a number of
specialized I/O resources which are associated with the
Dallas High–Speed micro core. These features are
described in this section.
5.1 PROGRAMMABLE TIMERS
Three programmable timers are included which are
compatible with the standard 80C52. All of the functions
are duplicated and all of the control bits and registers
associated with these functions are in their standard
locations. The standard operating modes of each timer
are fully described in the Dallas High Speed Micro
User’s Guide.
There is one important difference between the Dallas
High Speed Micro Core and the 8051 regarding timers.
The original 8051 used 12 clocks per cycle for timers as
well as for machine cycles. The High Speed Micro archi-
tecture normally uses 4 clocks per machine cycle. How-
ever, in the area of timers and serial port, the High
Speed Micro will default to 12 clocks per cycle on reset.
This allows existing code with real–time dependencies
such as baud rates to operate properly.
If an application needs higher speed timers or serial
baud rates, the user can select individual timers to run at
the 4 clock rate. The Clock Control register (CKCON;
8Eh) determines these timer speeds. When the relevant
CKCON bit is a logic 1, the High Speed Micro core uses
4 clocks per cycle to generate timer speeds. When the
bit is a 0, the High Speed Micro core uses 12 clocks for
timer speeds. The reset condition is a 0. CKCON.5
selects the speed of Timer 2. CKCON.4 selects Timer 1
and CKCON.3 selects Timer 0. Note that unless a user
desires very fast timing, it is unnecessary to alter these
bits. Note that the timer controls are independent.
5.2 SERIAL PORT
The SEM provides a serial port (UART) that is identical
to the 80C52. The duplicate serial port implemented as
described in the Dallas High Speed Micro User’s Guide
is not present. Operation of the original serial port,
which is called Serial Port 0, is fully described in the
User’s Guide.
5.3 WATCHDOG TIMER
To prevent software from losing control, the SEM
includes a programmable Watchdog Timer. The Watch-
dog is a free running timer that sets a flag if allowed to
reach a preselected time–out. It can be (re)started by
software.
A typical application is to select the flag as a reset
source. When the Watchdog times out, it sets its flag
which generates reset. Software must restart the timer
before it reaches its time–out or the processor is reset.
Software can select one of four time–out values. Then, it
restarts the timer and enables the reset function. After
enabling the reset function, software must then restart
the timer before its expiration or hardware will reset the
CPU. Both the Watchdog Reset Enable and the Watch-
dog Restart control bits are protected by a “Timed
Access” circuit. This prevents errant software from acci-
dentally clearing the Watchdog. Time–out values are
precise since they are a function of the crystal frequency
as shown below in Table 5–1. For reference, the time
periods at 25 MHz also are shown.
The Watchdog also provides a useful option for systems
that do not require a reset circuit. It will set an interrupt
flag 512 clocks before setting the reset flag. Software
can optionally enable this interrupt source. The interrupt
is independent of the reset. A common use of the inter-
rupt is during debug, to show developers where the
Watchdog times out. This indicates where Watchdog
must be restarted by software. The interrupt also can
serve as a convenient time–base generator or can
wake–up the processor.
The Watchdog function is controlled by the Clock Con-
trol (CKCON – 8Eh), Watchdog Control (WDCON –
D8h), and Extended Interrupt Enable (EIE – E8h) SFRs.
CKCON.7 and CKCON.6 are WD1 and WD0 respec-
tively and they select the Watchdog time–out period as
shown in Table 5–1. A complete operational description
for the Watchdog Timer is given in the Dallas High
Speed Micro User’s Guide.
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