DS80CH11 Datasheet, PDF (62/88 Pages) Dallas Semiconductor – System Energy Manager

DS80CH11
PWM CHANNEL BLOCK DIAGRAM Figure 11–3
PWM n CLOCK
8–BIT TIMER
REGISTER
ZERO COMPARATOR
MATCH COMPARATOR
BIT
PWn
DC
S
R
Q
BIT
PWn
OE
BIT
PWn
F
PWO.n
(P6.n ALT.
PIN FUINCTION)
BIT
PWn
T/C
11.5 PWM SPECIAL FUNCTION REGISTERS
A total of 12 SFR’s are used to control the four PWM
channels. The operation of these registers are summa-
rized below:
11.5.1 PW01CS / PW23CS – PWM 0, 1 / PWM 2, 3 Clock Select Registers
PW01CS; SFR ADDR.=0D5H
BIT 7
BIT 6
BIT 5
PW0S2
PW0S1
PW0S0
BIT 4
PW0EN
BIT 3
PW1S2
BIT 2
PW1S1
BIT 1
PW1S0
BIT 0
PW1EN
PW23CS; SFR ADDR.=0E5H
BIT 7
BIT 6
BIT 5
PW2S2
PW2S1
PW2S0
BIT 4
PW2EN
Read/Write Access: Unrestricted.
Initialization: 00H on any type of reset
PWnS2–0 – PWM n Clock Select Bits.
These three bits select one of four prescale frequencies
or an external pin as the input to the PWM n frequency
generator, which is then used as the clock source for
PWM channel n. The bit selections operate as follows:
BIT 3
PW3S2
BIT 2
PW3S1
BIT 1
PW3S0
BIT 0
PW3EN
PWnS2
0
0
0
0
1
PWnS1
0
0
1
1
X
PWnS0
0
1
0
1
X
PWM n CLOCK
FREQ.
t_MCLK* 1
t_MCLK* 4
t_MCLK* 16
t_MCLK* 64
PWI.n pin*
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