DS80CH11 Datasheet, PDF (50/88 Pages) Dallas Semiconductor – System Energy Manager

DS80CH11
7.8.2 ADCON2 – A/D Control Register 2
ADCON2; SFR ADDR.=0B3H
BIT 7
BIT 6
BIT 5
OUTCF
MUX2
MUX1
BIT 4
MUX0
BIT 3
APS3
BIT 2
APS2
BIT 1
APS1
BIT 0
APS0
Read/Write Access: Unrestricted.
Initialization: 00h on any type of reset
OUTCF – Output Conversion Format.
Selects whether the conversion output most–significant
8–bits or the most–significant 2–bits are presented in
the A/D MSB register. When OUTCF = 1, the MSB reg-
ister returns the upper 2 conversion bits, ADR8 and
ADR9 in bit locations 0 and 1 respectively. When
OUTCF = 0, the MSB register returns the upper 8 bits
with result bit ADR9 located in bit position 7 and result bit
ADR2 in bit position 0.
MUX2–0 – Multiplexor Select.
MUX2–0 select the A/D channel that will be sampled
and converted when the next conversion is initiated.
The table to the right shows the decoding.
MUX2 MUX1 MUX0 PIN A/D CHANNEL
0
0
0
AI0
Channel 0
0
0
1
AI1
Channel 1
0
1
0
AI2
Channel 2
0
1
1
AI3
Channel 3
1
0
0
AI4
Channel 4
1
0
1
AI5
Channel 5
1
1
0
AI6
Channel 6
1
1
1
AI7
Channel 7
APS3–0 – A/D Clock Prescale Select.
APS3–0 are used to determine the prescale setting from
the micro’s CPU clock to the A/D converter. The CPU
machine clock will be divided by the value of (N+1)
where N is the 4–bit value represented by APS3–0.
7.8.3 ADMSB – A/D Result Most Significant Byte
ADMSB; SFR ADDR.=0B4H
BIT 7
BIT 6
BIT 5
ADR9/
0
ADR8/
0
ADR7/
0
BIT 4
ADR6/
0
BIT 3
ADR5/
0
BIT 2
ADR4/
0
BIT 1
ADR3/
ADR9
BIT 0
ADR2/
ADR8
Read/Write Access: Unrestricted.
Initialization: 00h on any type of reset
Depending on the programming of the OUTCF bit, this
register contains either the most significant 8–bits or
2–bits of the conversion result. If OUTCF = 0 bits 7–0
contain bits 9–2, respectively, of the result. If
OUTCF=1, bits 7–2 contain 0, and bits 1 and 0 contain
result bits 9 and 8, respectively.
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