DS80CH11 Datasheet, PDF (57/88 Pages) Dallas Semiconductor – System Energy Manager

PMDIN1; SFR ADDR.=0BEH
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
DS80CH11
BIT 0
PMDIN2; SFR ADDR.=0F6H
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Read/Write Access: Read only.
Initialization: Undefined on any type of reset
Each input data register (KBDIN, PMDIN1 or PMDIN2)
is a read–only register to the SEM and a write–only reg-
ister to the host. The associated input buffer full flag
(KIBF, PIBF1 or PIBF2) will be set when the host CPU
writes to one of the input buffers. The SEM can enable
an “input buffer full” interrupt on any port by setting the
associated interrupt enable bit (EKB, EPB1 or EPB2).
Upon interrupt, the SEM’s firmware should check to see
if the incoming byte is a command or data by reading the
command/data flag, i.e., KC/D, PC/D1 or PC/D2, in the
status register followed by a read of the input data regis-
ter. The contents of the input data registers are unaf-
fected by any type of reset.
9.4 KBSTAT / PMSTAT1/PMSTAT2 – STATUS REGISTERS
KBSTAT; SFR ADDR.=0ADH
BIT 7
BIT 6
BIT 5
KST7
KST6
KST5
BIT 4
KST4
BIT 3
KC/D
BIT 2
KST2
BIT 1
KIBF
BIT 0
KOBF
PMSTAT1; SFR ADDR.=0BDH
BIT 7
BIT 6
BIT 5
P1ST7
P1ST6
P1ST5
BIT 4
P1ST4
BIT 3
PC/D1
BIT 2
P1ST2
BIT 1
PIBF1
BIT 0
POBF1
PMSTAT2; SFR ADDR.=0F5H
BIT 7
BIT 6
BIT 5
P2ST7
P2ST6
P2ST5
BIT 4
P2ST4
Read/Write Access: Unrestricted.
Initialization: XXXXXX00B on any type of reset
The operation of the bits in the status registers of both
ports are summarized below:
BIT 3
PC/D2
BIT 2
P2ST2
BIT 1
PIBF2
BIT 0
POBF2
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