DS80CH11 Datasheet, PDF (21/88 Pages) Dallas Semiconductor – System Energy Manager

INSTRUCTION SET SUMMARY Table 3–1 (cont’d)
Bit Manipulation
Instructions:
CLR C
1
4
ANL C, bit
2
CLR bit
2
8
ANL C, bit
2
SETB C
1
4
ORL C, bit
2
SETB bit
2
8
ORL C, bit
2
CPL C
1
4
MOV C, bit
2
CPL bit
2
8
MOV bit, C
2
Program Branching
Instructions:
ACALL addr 11
2
12
CJNE A, direct, rel
3
LCALL addr 16
3
16
CJNE A, #data, rel
3
RET
1
16
CJNE Rn, #data, rel
3
RETI
1
16
CJNE @ Ri, #data, rel
3
AJMP addr 11
2
12
NOP
1
LJMP addr 16
3
16
JC rel
2
SJMP rel
2
12
JNC rel
2
JMP @A+DPTR
1
12
JB bit, rel
3
JZ rel
2
12
JNB bit, rel
3
JNZ rel
2
12
JBC bit, rel
3
DJNZ Rn, rel
2
12
DJNZ direct, rel
3
16
DS80CH11
8
8
8
8
8
8
16
16
16
16
4
12
12
16
16
16
The Table above shows the speed for each class of
instruction. Note that many of the instructions have mul-
tiple opcodes. There are 255 opcodes for 111 instruc-
tions. Of the 255 opcodes, 159 are three times faster
than the original 80C32. While a system than empha-
sizes those instructions will see the most improvement,
the large total number that receive a three to one
improvement assure a dramatic speed increase for any
system. The speed improvement summary is provided
below.
3.3 SPEED IMPROVEMENT
The following table summarizes the speed improve-
ment of the High Speed Micro core over a standard 12
clock / machine cycle 8052 device.
#Opcodes
159
51
43
2
255
Speed Improvement
3.0 x
1.5 x
2.0 x
2.4 x
Average: 2.5
3.4 INSTRUCTION SET ADDITIONAL
REFERENCES
The user should refer to the Dallas High Speed Micro
User’s Guide for a complete description of the instruc-
tion set including its address modes, coding, and timing
for the SEM.
3.5 RESET
The High–Speed Micro has three ways of entering a
reset state:
• Power–On / Fail Reset
• Watchdog Timer Reset
• External Reset
The operation of the CPU timing and states during a
reset are documented in the Dallas High Speed Micro
User’s Guide under the “Reset Conditions” section. The
Watchdog Timer reset is documented in the Watchdog
Timer section of the Dallas High Speed Micro User’s
Guide. The operation of the Power–On / Fail reset is
described in the Power Management section of this doc-
ument.
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