DS80CH11 Datasheet, PDF (39/88 Pages) Dallas Semiconductor – System Energy Manager

DS80CH11
The desired slave address is placed in the most signifi-
cant 7–bits and a “0” in the least significant bit (direction
bit position) indicating a write operation. Transmission
of this byte will begin immediately upon writing the byte.
After writing the byte, the firmware must clear the TSTAx
and STAx bits. The firmware can now exit the interrupt
service routine or otherwise wait until the initial byte is
transmitted.
When the slave address and direction bit have been
sent and a positive acknowledge bit received back from
the slave, the TXIx bit will be set, indicating the transmis-
sion is complete. At this point the firmware can load the
first data byte into the transmit buffer and then clear the
TXIx bit. Because transmit mode is now in effect, clear-
ing TXIx causes the hardware to load the contents of the
buffer into the shift register. Therefore loading the buffer
before clearing TXIx will insure that the hardware will not
load the previous byte into the shift register and thereby
re–transmit it. Subsequent data bytes can be success-
fully transmitted each time TXIx is set by repeating the
above procedure. In the event that a negative acknowl-
edge bit is received back from the slave after sending
any bytes, the transmission can be aborted by issuing a
repeat START or STOP condition as described below.
As shown in the diagram, a repeat start condition can be
sent following the transmission of a data byte. In this
case the firmware should first set STAx to a 1 after
detecting that the TXIx flag is set. Since the port logic
has control of the bus, a repeat START condition will be
issued immediately, resulting in TSTAx being set to 1.
The firmware must then reset TSTAx, write the next
slave address and direction bit (0 = master transmit) to
the transmit buffer, and clear TXIx to 0. This sequence
will insure that the repeat start is sent before the data
containing the slave address is transmitted. Finally, the
STAx bit should be cleared to 0 so that another repeat
START will not be sent following the slave address byte.
Subsequent data bytes can then be transmitted as
described above.
When TXIx is set after the last byte of data has been
transmitted, a STOP condition can be issued by setting
the STOx bit to a 1. The TXIx bit must be cleared at this
point by firmware; this action will not cause any addi-
tional data to be sent since the port will be in receive
mode as a result of setting STOx. After the STOP condi-
tion is sent, the STOx bit will be automatically cleared
and X/Rx will be cleared to 0.
In the Master transmit mode, the arbitration logic checks
that every transmitted logic 1 actually appears as a logic
1 on the 2–Wire bus. If another device on the bus over-
rules a logic 1 and pulls the SDAx line low, arbitration is
lost, and the port logic immediately changes from Mas-
ter transmit mode to Slave Receive mode. The port
logic will continue to output clock pulses on SCLx until
transmission of the current serial byte is complete. At
the completion of the byte, the ARLx bit will be set to a 1.
The resulting transmitted serial word from the master
which won the arbitration will be available in the receive
buffer. If arbitration was lost during the transmission of
the slave address and the resulting address matches
the port’s programmed slave address in 2WSADRx,
then the ADMx bit will also be set to 1.
6.3.2 Master Receive
Figure 6–5 illustrates Master Receive operation. In
Master Receive mode, the SEM is configured as a mas-
ter and one or more data bytes are received from a slave
device.
The transfer is initiated as in the Master Transmit mode,
beginning with either a start condition or a repeat start
condition, followed by the transmission of the slave
address. However, in this case the direction bit should
be set to a 1 to signal Master Receive operation.
When the acknowledge bit for the slave address is
sampled, the TXIx bit will be set to a 1 and ACKSx bit will
reflect the state of the bit returned from the slave. Since
the direction bit was set to 1, the X/Rx bit will be cleared
to 0 indicating receive operation is now in effect. The
TXIx bit must be cleared to 0 by firmware to remove the
interrupt condition. No further bytes will be transmitted
in the packet since the port logic is in receive mode.
If it is desired to return a positive acknowledge bit upon
the receipt of subsequent data byte(s), the ANAKx bit
should be cleared to 0. Upon the receipt of the data
byte, the RXIx bit will be set at the time the acknowledge
bit is transmitted. The firmware should read the incom-
ing byte from the receive buffer register followed by a
clear of RXIx to 0. Subsequent incoming data bytes are
handled in the same manner.
After each byte is received and loaded into the receive
buffer and the RXIx flag cleared, the next byte will begin
to be shifted in immediately.
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