DS80CH11 Datasheet, PDF (12/88 Pages) Dallas Semiconductor – System Energy Manager

DS80CH11
PIN SYMBOL
DESCRIPTION
8 P9.0 (KSO.8) Port 9 / KSO.15–8: – I/O. Port 9 provides eight lines of open–drain psuedo–bi–direc-
7 P9.1 (KSO.9) tional I/O port pins. Typically, these lines are used for key–scan outputs.
6 P9.2 (KSO.10)
5 P9.3 (KSO.11)
4 P9.4 (KSO.12)
3 P9.5 (KSO.13)
2 P9.6 (KSO.14)
1 P9.7 (KSO.15)
60
P10.0
Port10: –I/O. Port 10 provides eight lines of general purpose Input or Output.
61
P10.1
62
P10.2
63
P10.3
64
P10.4
65
P10.5
66
P10.6
67
P10.7
41
PM1CS
Power Management #1 Chip Select: (Input, active low). This is a chip select signal
used to enable the power management #1 host interface port.
59
PM2CS
Power Management #2 Chip Select: (Input, active low). This is a chip select signal
used to enable the power management #2 host interface port.
107
PSEN
Program Store Enable: Output. This signal goes low when off–chip program memory
is being accessed via Ports 0 and 2. It is commonly connected to optional external ROM
memory as a chip enable. PSEN will provide an active low pulse and is driven high when
external ROM is not being accessed.
105
RST
Reset: Input, active high The RST input pin contains a Schmitt voltage input to recog-
nize external active high Reset inputs. The pin also employs an internal pull–down
resistor to allow for a combination of wired OR external Reset sources. An RC is not
required for power–up, as the controller provides this function internally.
55
SD0
System Data Bus: (Bi–directional). SD7–0 are data bus lines used for data transfers
54
SD1
between the host processor and the keyboard interface buffer and power management
53
SD2
#1 and #2 interface buffers.
52
SD3
51
SD4
50
SD5
49
SD6
48
SD7
39
SMI1
System Management Interrupt #1: (Output, active low). This signal is driven low
when the power management #1 host interface data buffer contains data to be read by
the host. SMI1 will be returned to a High Level when host reads the power management
#1 data buffer register.
58
SMI2
System Management Interrupt #2: (Output, active low). This signal is driven low
when the power management #2, host interface data buffer contains data to be read by
the host. SMI2 will be returned to a high level when the host reads the power manage-
ment #2 data buffer register.
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