DS80CH11 Datasheet, PDF (37/88 Pages) Dallas Semiconductor – System Energy Manager

DS80CH11
BBx – Bus Busy
This bit is used to signal the microcontroller that the
2–Wire bus is currently in use either by another master
or by the microcontroller itself. It will be set at detection
(or transmission) of a START and will be reset at detec-
tion (or transmission) of STOP.
ADMx – ADdress Match
This bit is set to a 1 when an address has been received
which either matches the value stored in the Address
Register or is the General Call address (00H). The
received address is available in the receive buffer. RXIx
will also be set when an address is received. ADMx will
stay set until a STOP or repeat START is generated.
X/Rx – Xmit / Receive
When X/Rx is set to 1, the 2–Wire port has entered
transmit mode. When X/Rx is cleared to 0, receive
mode operation is signaled.
ACKSx – ACKnowledge Status
ACKSx reflects the state of the acknowledge bit at the
end of a byte transfer on the bus. If a positive acknowl-
edge was detected, ACKSx will be set to 1. If a negative
acknowledge is detected, ACKSx will be cleared to 0.
6.3 OPERATIONAL DESCRIPTION
A typical 2–Wire bus configuration is shown in Figure
6–2 and Figure 6–3 illustrates how a data transfer is per-
formed. Two types of data transfers are possible on the
2–Wire bus:
1. Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is
the slave address with the R/W bit set to 0 (write), fol-
lowed by a number of data bytes. The slave returns
an acknowledge bit after each received byte.
2. Data transfer from a slave transmitter to a master
receiver. The first byte is again the slave address,
this time with the R/W bit set to 1 (read). The slave
returns an acknowledge bit for this first byte. Next,
the slave will transmit the pre–determined number of
data bytes to the master. The master returns an
acknowledge bit after each byte is received for all
but the last byte. At the end of the last byte, the mas-
ter returns a negative acknowledge. This action sig-
nals the slave to stop transmitting.
In both types of transfers, the master generates all of the
serial clock pulses as well as the START and STOP
conditions. A transfer is ended with a STOP condition or
with a repeated START condition. Since a repeated
START condition is also the beginning of the next serial
transfer, the 2–Wire bus will not be released in this case.
Both on–chip 2–Wire ports support four modes of
operation: Master transmitter, Master receiver, Slave
transmitter, and Slave Receiver. Operating the ports in
these four modes is described in detail below. Following
any type of reset, both 2–Wire ports will be configured in
slave receive mode.
TYPICAL 2–WIRE BUS CONFIGURATION Figure 6–2
V_CC
R_P
R_P
SDA
SCL
P1.3 / SDA1 P1.2 / SCL1
P1.5 / SDA2 P1.4 / SCL2
SEM
DS1307
SERIAL RTC
DS1621
DIGITAL
THERMOMETER
8–BIT uC
w/ 2–Wire I/F
011200 37/88