DS80CH11 Datasheet, PDF (64/88 Pages) Dallas Semiconductor – System Energy Manager

DS80CH11
PW1FG; SFR ADDR.=0D7H
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PW2FG; SFR ADDR.=0E6H
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PW3FG; SFR ADDR.=0E7H
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Read/Write Access: Unrestricted.
Initialization: 00H on any type of reset
The PWM channel n operating frequency is derived
from the frequency selected by PWnS2–0 (described
above) divided by the value of (PWnFG) + 1. Thus if
(PWnFG) = 0, divisor is 1, (PWnFG) = 1, divisor = 2,
(PWnFG) = 2, divisor = 3, etc. This value is the reload
11.5.4 PWMn – PWM n Value Registers
PWM0; SFR ADDR.=0DEH
BIT 7
BIT 6
BIT 5
BIT 4
value for the frequency generator’s 8–bit auto–reload-
able timer. The timer’s sole purpose is to generate the
clocking frequency for PWM n and is not otherwise
accessible. The PWM frequency will be correct after
one reload has occurred.
BIT 3
BIT 2
BIT 1
BIT 0
PWM1; SFR ADDR.=0DFH
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PWM2; SFR ADDR.=0EEH
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
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