DS80CH11 Datasheet, PDF (53/88 Pages) Dallas Semiconductor – System Energy Manager

ACTIVITY MONITOR INPUTS Figure 8–1
RD_P7.n
DS80CH11
AMI.n
BIT
AMP.n
IOR
BIT ^IOW
AMQ.n
BIT
AME.n
ACTIVITY
MONITOR
INTERRUPT
WR_“0”_AMF.n
When one or more peripheral devices have been pow-
ered down due to inactivity, it may be desirable at that
time to enable interrupts to at least those devices.
When an access is attempted by the host, the SEM can
take the appropriate action to apply power to the periph-
RD_AMF.n
eral. During such time, the SEM can activate the SMI1
or SMI2 interrupt by writing to a power management
host interface output buffer register with a status word
reflecting the current condition.
8.3 AME – ACTIVITY MONITOR ENABLE REGISTER
AME; SFR ADDR.=092H
BIT 7
BIT 6
AME7
AME6
BIT 5
AME5
BIT 4
AME4
BIT 3
AME3
BIT 2
AME2
BIT 1
AME1
BIT 0
AME0
Read/Write Access: Unrestricted.
Initialization: 00h on any type of reset
When an AME bit is set to 1, it enables the correspond-
ing line of Port 7 as an activity monitor interrupt source.
An interrupt condition will exist when the associated
activity monitor flag bit is set (see below). When AME is
cleared to 0, the associated pin is disabled as an inter-
rupt source. The associated Port 7 latch bit must be set
to 1 when a pin is to be programmed as an activity moni-
tor input.
8.4 AMQ – ACTIVITY MONITOR QUALIFIER REGISTER
AMQ; SFR ADDR.=093H
BIT 7
BIT 6
AMQ7
AMQ6
BIT 5
AMQ5
BIT 4
AMQ4
BIT 3
AMQ3
BIT 2
AMQ2
BIT 1
AMQ1
BIT 0
AMQ0
Read/Write Access: Unrestricted.
Initialization: 00h on any type of reset
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