DS80CH11 Datasheet, PDF (66/88 Pages) Dallas Semiconductor – System Energy Manager

DS80CH11
12.0 MICROCONTROLLER POWER
MANAGEMENT
12.1 POWER–DOWN / POWER–UP
OPERATION
The SEM incorporates a complete on–chip power moni-
toring and control function which performs the following
tasks:
• Power Fail Reset generation
• Power Fail Warning interrupt
12.1.1 Microcontroller Power Fail Reset
The SEM incorporates a precision band–gap voltage
reference and internal monitoring circuit to determine if
VCC is out of tolerance. The power fail reset feature
operates completely without the need for external com-
ponents.
During a power up or power down condition, the SEM’s
CPU and its I/O circuitry are held in a reset state for the
entire time that VCC is below the VRST threshold. In
addition, the VRST pin is held low so that the rest of the
system can be held in a reset state during this time.
When VCC rises above the VRST level during a power
up condition, the internal monitor circuit manages a
restart of the SEM’s microcontroller as follows: First, the
crystal oscillator is enabled and a delay of 65536 CPU
clock cycles is executed in order to allow time for the
microcontroller clock oscillator to stabilize. Then, the
VRST pin is taken inactive and the microcontroller core
is released from the reset state and begins code execu-
tion at the reset vector location (0000h). Software can
then determine that a power–on reset has occurred by
reading the Power On Reset flag (WDCON.6) which will
be set to a 1. The software should clear the POR flag
after reading it so that the next reset source can be prop-
erly determined.
Slow Clock mode. This mode allows the processor to
continue functioning, yet save power compared with full
operation mode. The SEM also features several
enhancements to STOP mode that make it more useful.
12.2.1 Slow Clock Mode
The Slow Clock Mode offers a complete scheme of
reduced internal clock speeds that allow the CPU to
continue to run software but to use substantially less
power. During default operation, the SEM uses 4 clocks
per machine cycle. Thus the instruction cycle rate is
Clock / 4. At 25 MHz crystal speed, the instruction cycle
speed is 6.25 MHz (25/4). In Slow Clock Mode, the
microcontroller continues to operate but uses an inter-
nally divided version of the clock source. This creates a
lower power state without external components. It
offers a choice of two reduced instruction cycle speeds
(and two clock sources – discussed below). The
speeds are (Clock / 64) and (Clock / 1024).
The microcontroller firmware is the only mechanism that
can invoke the Slow Clock Mode. Table 12–1 illustrates
the instruction cycle rate in Slow Clock Mode for several
common crystal frequencies. Since power consump-
tion is a direct function of operating speed, Slow Clock
Mode ( / 64) eliminates most of the power consumption
while still allowing a reasonable speed of processing.
Slow Clock Mode ( / 1024) runs very slow and provides
the lowest power consumption without stopping the
CPU. This is illustrated in Table 12–2.
Note that Slow Clock Mode provides a lower power
condition than IDLE mode. This is because in IDLE, all
clocked functions such as timers run at a rate of crystal
divided by 4. Since wake–up from Slow Clock Mode is
as fast as or faster than from IDLE and Slow Clock Mode
allows the CPU to operate (even if doing NOPs), there is
little reason to use IDLE in new designs.
12.2 LOW POWER OPERATING MODES
Along with the standard IDLE and power down (STOP)
modes of the standard 80C52, the SEM provides the
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