DS80CH11 Datasheet, PDF (33/88 Pages) Dallas Semiconductor – System Energy Manager

DS80CH11
6.0 2–WIRE SERIAL INTERFACE
6.1 INTRODUCTION
The SEM provides two industry standard 2–Wire serial
interfaces for processor–processor and processor–
slave bi–directional communication. The major fea-
tures of these buses include:
• Only two signal lines are required per bus: a serial
clock line (SCL) and a serial data line (SDA).
• Each device connected to the bus is software
addressable by a unique address.
• Masters can operate as Master–transmitter or Mas-
ter–receiver.
• Multiple master capability via collision detection and
arbitration to prevent data corruption if two or more
masters simultaneously initiate a data transfer.
• Serial clock synchronization allows devices with dif-
ferent bit rates to communicate via the same serial
bus.
• Devices can be added to or removed from the bus
without affecting any other circuit on the bus.
Both on–chip 2–Wire ports support four modes of
operation: Master transmitter, Master receiver, Slave
transmitter, Slave receiver. Byte–oriented data trans-
port, clock generation, address recognition, and bus
control arbitration are all performed by the hardware.
Double–buffering is provided on receive, allowing a full
word time to service the port during multiple byte data
transfers.
Figure 6–1 is a block diagram which illustrates the hard-
ware of both 2–Wire serial ports. For simplicity “x” rep-
resents 1 for Port 1 and 2 for Port 2.
2–WIRE SERIAL PORT BLOCK DIAGRAM Figure 6–1
INTERNAL
DATA BUS
R/W
09AH
0DAH
2WSADRx – ADDRESS
EN ^REGISTER
ADDRESS
COMPARE
R/W
09DH
0D9H
2WCONx – CONTROL
EN ^REGISTER
t_{MCLK R/W}
09CH
0D3H
DIVIDE BY
8 PRESCALE
2WFSx – FREQUENCY
EN
SELECT
DIVIDE BY
RELOAD VALUE
R/W
09EH
0DAH
RD
09FH
0DBH
2WSTAT1x – STATUS
EN REGISTER
2WSTAT2x – STATUS
EN REGISTER
RD
09BH
0D2H
2WDATx – RECEIVE
EN ^{DATA BUFFER}
WR
09BH
0D2H
DOUT _SHIFT
EN ^REGISTER
MSB
DIN
LSB
ACK
TIMING &
CONTROL
LOGIC
ARBITRATION
LOGIC
SERIAL
CLOCK GEN.
SDAx
PIN
SCLx
PIN
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