DS80CH11 Datasheet, PDF (71/88 Pages) Dallas Semiconductor – System Energy Manager

DS80CH11
SLOW CLOCK MODE CONTROL AND STATUS BIT SUMMARY Table 12–3
BIT NAME LOCATION
FUNCTION
RESET
WRITE ACCESS
XT/RG
EXIF.3
Control. XT/RG=1, runs from crystal or
external clock; XT/RG=0, runs from internal
Ring Oscillator.
X 0 to 1 only when
XTUP=1 and XTOFF=0
RGMD
EXIF.2
Status. RGMD=1, CPU clock = ring;
RGMD=0, CPU clock = crystal.
0 None
CD1, CD0
PMR.7,
PMR.6
Control. CD1,0=01, 4 clocks; CS1,0=10,
Slow Clock Mode 1; CD1,0=11,
Slow Clock Mode 2.
0, 1 Write CD1,0=10 or 11
only from CD1,0=01
SWB
PMR.5
Control. SWB=1, hardware invokes switch-
back to 4 clocks, SWB=0, no hardware
switchback.
0 Unrestricted
XTOFF
PMR.3
Control. Disables crystal operation after ring
is selected.
0 1 only when XT/RG=0
PIP
STATUS.7 Status. 1 indicates a power–fail interrupt in
service.
0 None
HIP
STATUS.6 Status. 1 indicates high priority interrupt in
service.
0 None
LIP
STATUS.5 Status. 1 indicates low priority interrupt in
service.
0 None
XTUP
STATUS.4 Status. 1 indicates that the crystal has stabi-
lized.
1 None
SPTA0 STATUS.1 Status. Serial transmission on serial port 0.
0 None
SPRA0 STATUS.0 Status. Serial word reception on serial port 0. 0 None
12.2.2 IDLE MODE
Setting the lsb of the Power Control register (PCON;
87h) invokes the IDLE mode. IDLE will leave internal
clocks, serial port and timers running. Power consump-
tion drops because the memory is not being accessed.
Since clocks are running, the IDLE power consumption
is a function of crystal frequency. It should be approxi-
mately 1/2 of the operational power at a given fre-
quency. The CPU can exit the IDLE state with any inter-
rupt or a reset. IDLE is available for backward software
compatibility. The system can now reduce power con-
sumption to below IDLE levels by using Slow Clock
Mode / 64 or / 1024 and running NOPs .
12.2.3 STOP MODE AND ENHANCEMENTS
Setting bit 1 of the Power Control register (PCON; 87h)
invokes the STOP mode. STOP mode is the lowest
power state since it turns off all internal clocking. The
ICC of a standard STOP mode is approximately 1 uA
(but is specified in the Electrical Specifications). The
CPU will exit STOP mode from an external interrupt or a
reset condition. Internally generated interrupts (timer,
serial port, watchdog) are not useful since they require
clocking activity.
The SEM provides two enhancements to the STOP
mode. The SEM incorporates a band–gap reference
which is used to determine Power–fail Interrupt and
Reset thresholds and to provide a reference for the on–
chip A/D converter. The default state is that the band–
gap reference is off while in STOP mode. This allows
the extremely low power state mentioned above. A user
can optionally choose to have the band–gap enabled
during STOP mode. With the band–gap reference
enabled, PFI and Power–fail reset are functional and
are valid means for leaving STOP mode. This allows
software to detect and compensate for a brown–out or
power supply sag, even when in STOP mode. In this
condition, ICC will be approximately 100 uA compared
with 1 uA with the band–gap off.
If a user does not require a Power–fail Reset or Interrupt
while in STOP mode, the band–gap can remain dis-
abled. In addition, the VRST output pin will be at a low
(active) level. In this manner, the SEM and the rest of
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