DS80CH11 Datasheet, PDF (42/88 Pages) Dallas Semiconductor – System Energy Manager

DS80CH11
lowed by the transmission of the SEM’s slave address
with the direction bit set to 1. This byte will be shifted in
and loaded into the receive buffer register at the time the
acknowledge bit is returned to the master, resulting in
RXIx being set to 1. In addition, an address match
condition will occur as indicated by the ADMx flag
set to 1.
SLAVE TRANSMIT OPERATION TIMING Figure 6–7
ÇÇÉÉÇÇÉÉÉÉÇÇÉÉÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ SDAx/SCLx
S
(Sr)
SLAVE ADDR.
R/W
A DATA
A DATA
A DATA
A
P
1
X/Rx BIT
ADMx BIT
DATA BUF:
WRITE
READ
RXIx BIT
TXIx BIT
ACKSx BIT
RSTOx BIT
Upon detecting these flags, the firmware should
respond by reading the receive buffer in order to deter-
mine if the programmed slave address or the general
call address was received. Following the read of the
buffer, the RXIx flag must be cleared. Also at this time
the firmware should insure that the 2WIFx bit is cleared
to 0, so that the interrupt flag will be set in response to
subsequent received data byte(s) and STOP condition.
If the programmed slave address was received, the
firmware can now send the first data byte by a write to
the transmit buffer. After the first data byte is transmitted
and the acknowledge bit received, the TXIx flag will be
set to 1. If the acknowledge bit ACKSx is returned as a
1, the next byte can be loaded into the transmit buffer
and the TXIx bit cleared. Successive bytes can be han-
dled in the same manner. Whenever any data is trans-
mitted from the 2–Wire port, the byte actually trans-
ferred on the bus will be shifted back in and loaded into
the receive buffer.
If the acknowledge bit ACKSx is returned as a 0 on a
transmitted byte, then the master is signaling this as the
last data byte in the packet. In this event, the X/Rx bit will
be automatically cleared to 0 and the firmware should
not write any more data bytes to the transmit buffer. The
TXIx bit must be cleared at this point by firmware; this
action will not cause any additional data to be sent since
the port is now in receive mode.
When the last byte of data has been sent, the bus mas-
ter will issue a STOP condition, which will result in the
RSTOx bit set to a 1. At this time, the port hardware
returns to the not–addressed slave mode.
011200 42/88