DS80CH11 Datasheet, PDF (60/88 Pages) Dallas Semiconductor – System Energy Manager

DS80CH11
11.0 PULSE WIDTH MODULATORS
11.1 FUNCTIONAL OVERVIEW
The SEM includes four independent timer channels
which can generate pulse–width modulated outputs. All
four pulse width modulator channels incorporate a clock
selector which generates an independent clock source
for each channel. As a result, an independent clock fre-
quency can be selected for each pulse width modulator.
Each pulse width modulator is capable of generating a
waveform which has a programmable duty cycle of
n/256% where 0<n<255. Figure 11–1 is a block diagram
illustrating the four–channel pulse width modulator
function.
PWM BLOCK DIAGRAM Figure 11–1
*1
*4
PRESCALER
*16
*64
t_MCLK
(uC MACHINE CLOCK)
PWM 0
CLOCK GENERATOR
PWM 1
CLOCK GENERATOR
PWM 2
CLOCK GENERATOR
PWM 3
CLOCK GENERATOR
PWM 0
PULSE GENERATOR
PWM 1
PULSE GENERATOR
PWM 2
PULSE GENERATOR
PWM 3
PULSE GENERATOR
PWO.0 (P6.0 ALT. FUNCITON)
PWI.0 (P6.4 ALT. FUNCITON)
PWO.1 (P6.1 ALT. FUNCITON)
PWI.1 (P6.5 ALT. FUNCITON)
PWO.2 (P6.2 ALT. FUNCITON)
PWO.3 (P6.3 ALT. FUNCITON)
11.2 PRESCALER
This block creates and distributes four clock outputs
which are supplied to the clock selectors. The prescaler
takes the microcontroller machine clock and divides it to
produce reduced speed frequencies. The CPU
machine clock period (t_MCLK) is the oscillator clock
period (t_CLK) multiplied times 4, 64, or 1024 as deter-
mined by the programming of the system clock divider
bits (CD1, CD0) in the PMR register. The prescaler pro-
vides four frequencies: t_MCLK *1, t_MCLK *4, t_MCLK *16,
t_MCLK *64. These frequencies are free running and are
not specifically enabled or selected. They are simulta-
neously available to the four PWM clock selectors as
described below.
11.3 PWM CLOCK GENERATORS
Within the PWM function there are four identical but
separate clock generators for each of the four indepen-
dent PWM channels. The clock generator function is
illustrated in Figure 11–2. All four clock generators
accept the four prescaler clock outputs and an external
pin as inputs. PWI.0 may be selected as the clock gen-
erator input for PWM channels 0 and 2, and PWI.1 may
be selected as the clock generator input for channels 1
and 3. If PWI.1 or PWI.0 are to be selected as the clock
input source, then associated port bit latch (P6.5 or
P6.4) must be programmed as an input (set to 1) in order
to enable the alternate function of these pins. If
selected, PWI.1 and PWI.0 will be sampled and syn-
chronized to internal microcontroller timing as with other
8051 compatible timer inputs.
Thus, for all clock generators there are five choices for
the input clock source, which is used to drive an 8–bit
auto–reloadable counter. This counter output provides
a divide by N+1 selectable frequency for the PWM chan-
nel, where N is the value programmed into the counter
register. When a value of 00H is programmed into the
counter the input clock frequency will be passed through
as the clock output to the channel’s pulse genera-
tor. A value of 0FFH will result in the clock input being
divided by 256 and output to the pulse generator.
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