DS80CH11 Datasheet, PDF (67/88 Pages) Dallas Semiconductor – System Energy Manager

DS80CH11
SLOW CLOCK MODE INSTRUCTION CYCLE RATE Table 12–1
CRYSTAL SPEED
FULL SPEED
(4 CLOCKS)
SLOW CLOCK
(64 CLOCKS)
1.8432 MHz
460.8 KHz
28.8 KHz
11.0592 MHz
2.765 MHz
172.8 KHz
22 MHz
5.53 MHz
345.6 KHz
25 MHz
6.25 MHz
390.6 KHz
SLOW CLOCK
(1024 CLOCKS)
1.8 KHz
10.8 KHz
21.6 KHz
24.4 KHz
SLOW CLOCK MODE OPERATING CURRENT ESTIMATES Table 12–2
CRYSTAL SPEED
FULL SPEED
(4 CLOCKS)
SLOW CLOCK
(64 CLOCKS)
1.8432 MHz
3.1 mA
1.2 mA
3.57 MHz
5.3 mA
1.6 mA
11.0592 MHz
15.5 mA
4.8 mA
16 MHz
21 mA
7.1 mA
22 MHz
25.5 mA
8.3 mA
25 MHz
31 mA
9.7 mA
SLOW CLOCK
(1024 CLOCKS)
1.0 mA
1.1 mA
4.0 mA
6.0 mA
6.5 mA
8.0 mA
12.2.1.1 Crystaless Slow Clock Mode
A major component of power consumption in Slow
Clock Mode is the crystal amplifier circuit. The SEM
allows the user the option to switch CPU operation to an
internal ring oscillator and turn off the crystal amplifier.
The CPU would then have a clock source of approxi-
mately 4 MHz, divided by either 4, 64, or 1024. The ring
oscillator as a time base is not precise and as a result
software can not perform precision timing. However,
this mode allows an additional saving of between 0.5
and 6.0 mA depending on the actual crystal frequency.
While this saving is of little use when running at 4 clocks
per instruction cycle, it makes a major contribution when
running in Slow Clock Mode.
12.2.1.2 Slow Clock Mode Operation
Software invokes the Slow Clock Mode by setting the
appropriate bits in the SFR area. The basic choices are
divider speed and clock source. There are three speeds
(4, 64, 1024) and two clock sources (crystal, ring). Both
the decisions and the controls are separate. Software
will typically select the clock speed first. Then, it will per-
form the switch to ring operation if desired. Lastly, soft-
ware can disable the crystal amplifier if desired.
There are two ways of exiting Slow Clock Mode. Soft-
ware can remove the condition by reversing the proce-
dure that invoked Slow Clock Mode or hardware can
(optionally) remove it. To resume operation at a divide
by 4 rate under software control, simply select 4 clocks
per cycle, then crystal based operation if relevant.
When disabling the crystal as the time base in favor of
the ring oscillator, there are timing restrictions
associated with restarting the crystal operation. Details
are described below.
There are three registers containing bits that are con-
cerned with Slow Clock Mode functions. They are
Power Management Register (PMR; C4h), Status
(STATUS; C5h), and External Interrupt Flag (EXIF; 91h)
12.2.1.3 Clock Divider
Software can select the instruction cycle rate by select-
ing bits CD1 (PMR.7) and CD0 (PMR.6) as follows:
CD1
0
0
1
1
CD0
0
1
0
1
Cycle rate
Reserved
4 clocks (default)
64 clocks
1024 clocks
The selection of instruction cycle rate will take effect
after a delay of one instruction cycle. Note that the clock
divider choice applies to all functions including timers.
Since baud rates are altered, it will be difficult to conduct
serial communication while in Slow Clock Mode. There
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