DS80CH11 Datasheet, PDF (77/88 Pages) Dallas Semiconductor – System Energy Manager

DS80CH11
13.3.2 MOVX USING STRETCH MEMORY CYCLES
(0°C to 70°C; V_CC=5.0 ± 10%)
VARIABLE CLOCK
PARAMETER
SYMBOL
MIN
MAX
UNITS STRETCH
Data Access ALE Pulse Width
t_LHLL2
1.5t_CLCL–5
ns
2t_CLCL–5
Address Hold after ALE Low for
t_LLAX2
0.5t_CLCL–5
ns
MOVX Write
t_CLCL–5
RD Pulse Width
t_RLRH
2t_CLCL–5
ns
t_MCS–10
WR Pulse Width
t_WLWH
2t_CLCL–5
ns
t_MCS–10
RD Low to Valid Data In
t_RLDV
2t_CLCL–20
ns
t_MCS–20
Data Hold after Read
t_RHDX
0
ns
Data Float after Read
t_RHDZ
t_CLCL–5
ns
2t_CLCL–5
ALE Low to Valid Data In
t_LLDV
2.5t_CLCL–20
ns
t_MCS+t_CLCL–40
Port 0 Address to Valid Data In
t_AVDV1
3t_CLCL–20
ns
t_MCS+1.5t_CLCL–20
Port 2 Address to Valid Data In
t_AVDV2
3.5t_CLCL–20
ns
t_MCS+2t_CLCL–20
ALE Low to RD or WR Low
t_LLWL
0.5t_CLCL–5
0.5t_CLCL+5
ns
t_CLCL–5
t_CLCL+5
Port 0 Address to RD or WR Low
t_AVWL1
t_CLCL–5
ns
2t_CLCL–5
Port 2 Address to RD or WR Low
t_AVWL2
1.5t_CLCL–5
ns
2.5t_CLCL–5
Data Valid to WR Transition
t_QVWX
–5
ns
Data Hold after Write
t_WHQX
t_CLCL–5
ns
2t_CLCL–5
RD Low to Address Float
t_RLAZ
–0.5t_CLCL–5
ns
RD or WR High to ALE High
t_WHLH
0
10
ns
t_CLCL–5
t_CLCL+5
t_MCS=0
t_MCS>0
t_MCS=0
t_MCS>0
t_MCS=0
t_MCS>0
t_MCS=0
t_MCS>0
t_MCS=0
t_MCS>0
t_MCS=0
t_MCS>0
t_MCS=0
t_MCS>0
t_MCS=0
t_MCS>0
t_MCS=0
t_MCS>0
t_MCS=0
t_MCS>0
t_MCS=0
t_MCS>0
t_MCS=0
t_MCS>0
t_MCS=0
t_MCS>0
t_MCS=0
t_MCS>0
NOTE:
t_MCS is a time period related to the Stretch memory cycle selection. The following table shows the value of t_MCS for
each Stretch selection.
M2
M1
M0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
MOVX CYCLES
2 machine cycles
3 machine cycles (default)
4 machine cycles
5 machine cycles
6 machine cycles
7 machine cycles
8 machine cycles
9 machine cycles
t_MCS
0
4 t_CLCL
8 t_CLCL
12 t_CLCL
16 t_CLCL
20 t_CLCL
24 t_CLCL
28 t_CLCL
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