DS80CH11 Datasheet, PDF (76/88 Pages) Dallas Semiconductor – System Energy Manager

DS80CH11
7. During a 0 to 1 transition, a one–shot drives the ports hard for two oscillator clock cycles. This measurement
reflects port in transition mode. In addition, this specification applies to any of the Port 6.0–Port 6.3 pins when
the associated PWM channel is enabled.
8. Ports 1, 2, and 3 source transition current when being pulled down externally. Current reaches its maximum at
approximately 2V.
9. 0.45<V_IN<V_CC. Not a high impedance input. This port is a weak address holding latch in Bus Mode. Peak current
occurs near the input transition point of the latch, approximately 2V.
10. 0.45<V_IN<V_CC. RST=V_CC. This condition mimics operation of pins in I/O mode.
13.3 MICROCONTROLLER AC ELECTRICAL
CHARACTERISTICS
13.3.1 EXTERNAL PROGRAM MEMORY
CHARACTERISTICS
25 MHz
PARAMETER
SYMBOL MIN
Oscillator Frequency
1/t_CLCL
0
ALE Pulse Width
t_LHLL
55
Port 0 Address Valid to ALE Low
t_AVLL
15
Address Hold after ALE Low
t_LLAX1
15
ALE Low to Valid Instruction In
t_LLIV
ALE Low to PSEN Low
t_LLPL
15
PSEN Pulse Width
t_PLPH
75
PSEN Low to Valid Instruction In
t_PLIV
Input Instruction Hold after PSEN
t_PXIX
0
Input Instruction Float after PSEN
t_PXIZ
Port 0 Address to Valid
Instruction In
t_AVIV1
Port 2 Address to Valid
Instruction In
t_AVIV2
MAX
25
80
60
35
100
115
PSEN Low to Address Float
t_PLAZ
0
(0°C to 70°C; V_CC=5.0 ± 10%)
VARIABLE CLOCK
MIN
MAX
UNITS
0
25
MHz
(3t_CLCL/2)–5
ns
(t_CLCL/2)–5
ns
(t_CLCL/2)–5
ns
2.5t_CLCL–20
ns
(t_CLCL/2)–5
ns
2t_CLCL–5
ns
2t_CLCL–20
ns
0
ns
t_CLCL–5
ns
3t_CLCL–20
ns
3.5t_CLCL–25
ns
0
ns
NOTES:
1. All signals rated over operating temperature.
2. All signals characterized with load capacitance of 80 pF except Port 0, ALE, PSEN, RD and WR with 100 pF.
3. Interfacing to memory devices with float times (turn off times) over 25 ns may cause contention. This will not dam-
age the parts, but will cause an increase in operating current.
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