DS80CH11 Datasheet, PDF (46/88 Pages) Dallas Semiconductor – System Energy Manager

DS80CH11
SAR A/D SIMPLIFIED BLOCK DIAGRAM Figure 7–2
ACLK
START
EOC
CONTROL
LOGIC
SUCCESSIVE
APPROXIMATION
REGISTER
2 _OFFSET
SAR [9..0]
RESOLUTION
ANALOG IN
REFHI
REFLO
10–BIT
SAMPLING
D/A CONVERTER
CVT
ZRO (SAMPLE)
–
COMP
+
7.5 CONVERSION TIME
An internal clock signal called ACLK is used to clock the
successive approximation logic in performing the A/D
conversion. ACLK is derived from the microcontroller
clock signal through divide–down logic. A total of 16
clock cycles are required to perform the conversion.
The minimum ACLK period is 1 µs, a faster clock can
result in erroneous results. At the other extreme, the
maximum clock period is 6.25 µs due the dynamic
nature of the internal sample–hold circuitry.
In order to meet these requirements and accommodate
a wide range of CPU clock frequencies a programmable
prescaler is provided to generate appropriate converter
clock (ACLK) from the CPU clock.
Based on the micro’s CPU clock, the ACLK frequency
can be set to one of 16 values via the four A/D clock
prescaler (APS) bits in the ADCON2 register. This
results in a conversion clock frequency as given by the
formula below:
t_ACLK = t_MCLK • (N+1)
where t_ACLK is the analog clock period, t_MCLK is the CPU
machine clock period, and N is the clock prescale value
ranging from 0 to 15 as programmed in the APS bits.
The CPU machine clock period is the oscillator clock
period (t_CLK) multiplied times 4, 64, or 1024 as deter-
mined by the programming of the system clock divider
bits (CD1, CD0) in the PMR register.
The resulting t_ACLK must meet the criteria of
1.00 µs < t_ACLK < 6.25 µs
Table 7–1 gives a set of conversion times at usable A/D
clock prescaler settings for a range of microcontroller
clock frequencies, assuming that the microcontroller
machine clock is at its default value of 4 crystal clock
periods.
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