DS80CH11 Datasheet, PDF (35/88 Pages) Dallas Semiconductor – System Energy Manager

DS80CH11
6.2.4 2WCONx – 2–Wire Control Registers
2WCON1; SFR ADDR.=09DH, 2WCON2; SFR ADDR.=0D9H
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
2WENx
STAx
STOx
2WIFx
BMMx
BIT 2
ANAKx
BIT 1
–
BIT 0
–
Read/Write Access: Unrestricted.
Initialization: 00H on any type of reset
If STAx is cleared to 0, no further START or repeat
START will be attempted.
The 2–Wire Control Register bits <7:2> can be read or
written by the microcontroller. Bit <1,0> are reserved for
future use and should be ignored by the firmware. Refer
to the bit description below for specific set/reset condi-
tions.
2WENx – 2–Wire Enable
When 0, the 2–Wire port is disabled. SCLx and SDAx
pins are off (high–Z), no internal processing or bus mon-
itoring is performed, and all internal registers are reset.
If SDAx and SCLx are left connected to the 2–Wire bus
with 2WENx = 0, the serial interface hardware will not
generate or respond to activity on the bus. Also when
2WENx = 0, SDAx and SCLx can be used as open drain
general purpose I/O port pins (P1.5, P1.3, P1.4, and
P1.2, respectively) and are accessible via the port 1
latch register.
When 2WENx = 1, the 2–Wire interface is enabled.
P1.5, P1.4, P1.3 and P1.2 port latches must be set to 1
in order for both serial interfaces, to operate.
STAx – 2–Wire Start
The firmware can generate a start or a repeat start
condition by setting STAx=1 with STOx=0. The hard-
ware will then wait for the bus to be free, and generate a
start condition on the bus in an attempt to gain control of
the bus as a master. If the start condition fails, or if the
port loses arbitration, the hardware will repeat its
attempt until it is successful as long as STAx=1. When
the START condition is successfully asserted, the
TSTAx flag will be set.
If the STAx bit remains set while in the master mode
throughout the time that a byte is being transmitted or
received, then a repeat START condition will be
asserted at the end of the byte transfer. Again, TSTAx
will be set when the repeat start is successfully
asserted.
STOx – 2–Wire Stop
If STOx=1 when the hardware has control of the bus as
a master, a stop condition is issued on the bus after the
transmit or receive of any byte currently in progress is
completed. When the STOP condition is transmitted on
the bus, the STOx flag will automatically be cleared to 0.
If both STAx and STOx are set in the master mode, the
STOP condition will be generated first. After the STOx
bit is cleared a START will be generated.
When STOx=0, no STOP condition is generated.
2WIFx – 2–Wire Interrupt Flags
2WIFx serves as the main interrupt flag bit for the
2–Wire port. If BMMx = 0, (in 2WCONx register) 2WIFx
is set to 1 whenever operating as a master or as an
addressed slave and one or more of the following inter-
rupt source bits in 2–Wire Status Register (2WSTAT1x)
are set (active): BERx, ARLx, RSTOx, TXIx, RXIx,
TSTAx.
When BMMx=1, the 2WIFx flag will be set when any of
the following source bits are set: BERx, ARLx, RSTOx,
TXIx, RXIx, TSTAx, RSTAx. Note that in this case
RSTAx also generates an interrupt.
Regardless of the state of the BMMx bit, the 2WIFx bit
will be cleared when all of its source bits are cleared.
BMMx – Bus Monitor Mode
When BMMx=0, the 2–Wire port will only generate inter-
rupts if it is operating as a master or being addressed as
a slave.
If bus monitoring is enabled with BMMx = 1, the port can
“listen” to (receive) packets sent from external masters
to external slaves on the 2–Wire bus. In this mode the
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