EP3SL50 Datasheet, PDF (78/341 Pages) Altera Corporation – Stratix III Device Handbook, Volume 2

1–68
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–51. EP3SL70 Column Pins Input Timing Parameters (Part 3 of 3)
I/O
Standard
Clock
Fast Model
C2
Industrial Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
t_su -0.732
GCLK
1.2-V HSTL
t_h 0.856
CLASS I
GCLK ^tsu ^-0.885
PLL
t_h 1.138
t_su -0.720
GCLK
1.2-V HSTL
t_h 0.844
CLASS II
GCLK ^tsu ^-0.873
PLL
t_h 1.126
GCLK ^{tsu -0.720}
t_h 0.844
3.0-V PCI
GCLK ^tsu ^-0.873
PLL
t_h 1.126
3.0-V
PCI-X
t_su -0.823
GCLK
t_h 0.945
GCLK ^tsu ^-0.976
PLL
t_h 1.227
-0.731
0.856
-0.885
1.138
-0.719
0.844
-0.873
1.126
-0.719
0.844
-0.873
1.126
-0.822
0.945
-0.976
1.227
-1.050 -1.145 -1.085 -1.037 -1.416 -1.145 -1.085 -1.037 -1.416 ns
1.222 1.338 1.303 1.245 1.616 1.338 1.303 1.245 1.616 ns
-1.291 -1.406 -1.533 -1.471 -1.865 -1.406 -1.533 -1.471 -1.865 ns
1.659 1.818 1.989 1.905 2.306 1.818 1.989 1.905 2.306 ns
-1.040 -1.134 -1.069 -1.021 -1.400 -1.134 -1.069 -1.021 -1.400 ns
1.212 1.327 1.287 1.229 1.600 1.327 1.287 1.229 1.600 ns
-1.281 -1.395 -1.517 -1.455 -1.849 -1.395 -1.517 -1.455 -1.849 ns
1.649 1.807 1.973 1.889 2.290 1.807 1.973 1.889 2.290 ns
-1.040 -1.134 -1.069 -1.021 -1.400 -1.134 -1.069 -1.021 -1.400 ns
1.212 1.327 1.287 1.229 1.600 1.327 1.287 1.229 1.600 ns
-1.281 -1.395 -1.517 -1.455 -1.849 -1.395 -1.517 -1.455 -1.849 ns
1.649 1.807 1.973 1.889 2.290 1.807 1.973 1.889 2.290 ns
-1.153 -1.263 -1.311 -1.265 -1.644 -1.263 -1.311 -1.265 -1.644 ns
1.326 1.459 1.532 1.474 1.849 1.459 1.532 1.474 1.849 ns
-1.394 -1.524 -1.762 -1.702 -2.093 -1.524 -1.762 -1.702 -2.093 ns
1.763 1.939 2.221 2.137 2.539 1.939 2.221 2.137 2.539 ns
Table 1–52 lists the EP3SL70 row pins input timing parameters for single-ended I/O
standards.
Table 1–52. EP3SL70 Row Pins Input Timing Parameters (Part 1 of 3)
I/O
Standard
Clock
Fast Model
Industrial Commercial
C2
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
GCLK ^tsu
3.3-V LVTTL
t_h
GCLK ^tsu
PLL _th
3.3-V
LVCMOS
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
GCLK ^tsu
t_h
3.0-V LVTTL
GCLK ^tsu
PLL _th
-0.811
0.925
0.937
-0.688
-0.811
0.925
0.937
-0.688
-0.817
0.931
0.931
-0.682
-0.836
0.962
0.945
-0.684
-0.836
0.962
0.945
-0.684
-0.847
0.973
0.934
-0.673
-1.185 -1.296 -1.513 -1.460 -1.732 -1.306 -1.513 -1.464 -1.763 ns
1.582 1.801 1.915 1.799 1.814 1.796 1.923 1.804 1.865 ns
1.371 1.505 1.747 1.679 1.951 1.526 1.756 1.693 1.982 ns
-1.185 -1.296 -1.513 -1.460 -1.732 -1.306 -1.513 -1.464 -1.763 ns
-1.185 -1.296 -1.513 -1.460 -1.732 -1.306 -1.513 -1.464 -1.763 ns
1.582 1.801 1.915 1.799 1.814 1.796 1.923 1.804 1.865 ns
1.371 1.505 1.747 1.679 1.951 1.526 1.756 1.693 1.982 ns
-1.182 -1.297 -1.516 -1.463 -1.735 -1.305 -1.518 -1.469 -1.768 ns
1.368 1.506 1.750 1.682 1.954 1.525 1.761 1.698 1.987 ns
-1.182 -1.297 -1.516 -1.463 -1.735 -1.305 -1.518 -1.469 -1.768 ns
1.585 1.800 1.912 1.796 1.811 1.797 1.918 1.799 1.860 ns
1.368 1.506 1.750 1.682 1.954 1.525 1.761 1.698 1.987 ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation