EP3SL50 Datasheet, PDF (113/341 Pages) Altera Corporation – Stratix III Device Handbook, Volume 2

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–103
Table 1–63. EP3SL110 Column Pins Output Timing Parameters (Part 6 of 7)
I/O
Standard
Clock
Fast Model
C2
Industrial
Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL= V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
SSTL-15
CLASS II
GCLK t_co
8mA _GCLK
PLL ^tco
GCLK t_co
16mA _GCLK
PLL ^tco
3.268
3.658
3.271
3.661
3.268
3.658
3.271
3.661
4.617 5.001 5.499 5.368 5.662 5.001 5.499 5.368 5.662 ns
5.193 5.634 6.187 6.029 6.411 5.634 6.187 6.029 6.411 ns
4.624 5.010 5.510 5.379 5.673 5.010 5.510 5.379 5.673 ns
5.200 5.643 6.198 6.040 6.422 5.643 6.198 6.040 6.422 ns
GCLK t_co 3.278
4mA
GCLK
PLL ^tco
3.668
3.278
3.668
4.619 5.001 5.497 5.366 5.660 5.001 5.497 5.366 5.660 ns
5.195 5.634 6.185 6.027 6.409 5.634 6.185 6.027 6.409 ns
GCLK t_co 3.271
6mA
GCLK
PLL ^tco
3.661
3.271
3.661
4.617 5.000 5.496 5.365 5.659 5.000 5.496 5.365 5.659 ns
5.193 5.632 6.184 6.026 6.408 5.632 6.184 6.026 6.408 ns
1.8-V
HSTL
CLASS I
GCLK t_co
8mA _GCLK
PLL ^tco
3.263
3.653
3.263
3.653
4.610 4.992 5.489 5.358 5.652 4.992 5.489 5.358 5.652 ns
5.185 5.625 6.177 6.019 6.401 5.625 6.177 6.019 6.401 ns
GCLK t_co
10mA _GCLK
PLL ^tco
3.266
3.656
3.266
3.656
4.613 4.996 5.493 5.362 5.656 4.996 5.493 5.362 5.656 ns
5.188 5.628 6.181 6.023 6.405 5.628 6.181 6.023 6.405 ns
GCLK t_co
12mA _GCLK
PLL ^tco
3.263
3.653
3.263
3.653
4.615 4.999 5.497 5.366 5.660 4.999 5.497 5.366 5.660 ns
5.191 5.632 6.185 6.027 6.409 5.632 6.185 6.027 6.409 ns
1.8-V
HSTL
CLASS II
GCLK t_co
16mA _GCLK
PLL ^tco
3.271
3.661
3.271
3.661
4.614 4.997 5.493 5.362 5.656 4.997 5.493 5.362 5.656 ns
5.190 5.629 6.181 6.023 6.405 5.629 6.181 6.023 6.405 ns
GCLK t_co 3.283
4mA
GCLK
PLL ^tco
3.673
3.283
3.673
4.628 5.011 5.508 5.377 5.671 5.011 5.508 5.377 5.671 ns
5.203 5.644 6.196 6.038 6.420 5.644 6.196 6.038 6.420 ns
GCLK t_co 3.279
6mA
GCLK
PLL ^tco
3.669
3.279
3.669
4.629 5.013 5.511 5.380 5.674 5.013 5.511 5.380 5.674 ns
5.204 5.645 6.199 6.041 6.423 5.645 6.199 6.041 6.423 ns
1.5-V
HSTL
CLASS I
GCLK t_co
8mA _GCLK
PLL ^tco
3.275
3.665
3.275
3.665
4.624 5.008 5.506 5.375 5.669 5.008 5.506 5.375 5.669 ns
5.200 5.641 6.194 6.036 6.418 5.641 6.194 6.036 6.418 ns
GCLK t_co
10mA _GCLK
PLL ^tco
3.268
3.658
3.268
3.658
4.617 5.001 5.499 5.368 5.662 5.001 5.499 5.368 5.662 ns
5.193 5.634 6.187 6.029 6.411 5.634 6.187 6.029 6.411 ns
GCLK t_co
12mA _GCLK
PLL ^tco
3.269
3.659
3.269
3.659
4.624 5.009 5.509 5.378 5.672 5.009 5.509 5.378 5.672 ns
5.200 5.642 6.197 6.039 6.421 5.642 6.197 6.039 6.421 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2