EP3SL50 Datasheet, PDF (34/341 Pages) Altera Corporation – Stratix III Device Handbook, Volume 2

1–24
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
Switching Characteristics
Table 1–26. DPA Lock Time Specifications for Stratix III Devices (Note 1), (2), (3) (Part 2 of 2)
Standard
Training
Pattern
Number of
Data
Transitions
in one
Repetition
of Training
Pattern
Number of
repetitions
per 256
Data
Transition
(4)
Condition (5)
Min
Typ
Max
10101010
8
Miscellaneous
01010101
8
without DPA
PLL calibration
256 data transitions
—
—
32
with DPA PLL
calibration
3×256 data transitions +
2×96 slow clock cycles
(6)
—
—
without DPA
PLL calibration
256 data transitions
—
—
32
with DPA PLL
calibration
3×256 data transitions +
2×96 slow clock cycles
(6)
—
—
Notes to Table 1–26:
(1) The DPA lock time is for one channel.
(2) One data transition is defined as a 0-to-1 or 1-to-0 transition.
(3) The DPA lock time stated in this table applies to both commercial and industrial grade.
(4) These are the number of repetitions for the stated training pattern to achieve 256 data transitions.
(5) Altera recommends PLL re-calibration for the situations below to guarantee DPA locking:
■ Sparse data transitions. For example: Repeating sequences of ten 1s and ten 0s.
■ 0 PPM frequency difference and/or 0° phase difference between the clock and data.
(6) Slow clock = data rate (Hz)/ Deserialization factor.
Figure 1–2 shows the DPA time specification with DPA PLL calibration enabled.
Figure 1–2. DPA Lock Time Specification with DPA PLL Calibration Enabled
rx_reset
rx_dpa_locked
DPA Lock Time
256 data
transitions
96 slow
clock cycles
256 data
transitions
96 slow
clock cycles
256 data
transitions
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation