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EP3SL50 Datasheet, PDF (320/341 Pages) Altera Corporation – Stratix III Device Handbook, Volume 2 | |||
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1â310
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Dedicated Clock Pin Timing
Table 1â141 to Table 1â201 list clock pin timing for Stratix III devices when the clock is
driven by the global clock, regional clock, periphery clock, and a PLL.
Table 1â141 lists the Stratix III clock timing parameters.
Table 1â141. Clock Timing Parameters for Stratix III Devices
Symbol
tCIN
tCOUT
tPLLCIN
tPLLCOUT
Parameter
Delay from the clock pad to the I/O input register
Delay from the clock pad to the I/O output register
Delay from the PLL inclk pad to the I/O input register
Delay from the PLL inclk pad to the I/O output register
EP3SL50 Clock Timing Parameters
Table 1â142 and Table 1â143 list the global clock timing parameters for EP3SL50
devices.
Table 1â142. EP3SL50 Column Pin Global Clock Timing Specifications
Parameter
tCIN
tCOUT
tPLLCIN
tPLLCOUT
Fast Model
Industrial
1.736
1.736
-0.018
-0.018
Commercial
1.737
1.737
-0.026
-0.026
C2
VCCL=
1.1 V
2.436
2.436
-0.261
-0.261
C3
VCCL=
1.1 V
2.691
2.691
-0.312
-0.312
C4
VCCL=
1.1 V
3.056
3.056
-0.251
-0.251
C4L
VCCL=
1.1 V
2.925
2.925
-0.230
-0.230
VCCL=
0.9 V
3.433
3.433
-0.011
-0.011
I3
VCCL=
1.1 V
2.691
2.691
-0.312
-0.312
I4
VCCL=
1.1 V
3.056
3.056
0.161
0.161
I4L
VCCL=
1.1 V
2.925
2.925
-0.230
-0.230
VCCL=
0.9 V
3.433
3.433
-0.011
-0.011
Units
ns
ns
ns
ns
Table 1â143. EP3SL50 Row Pin Global Clock Timing Specifications
Parameter
tCIN
tCOUT
tPLLCIN
tPLLCOUT
Fast Model
Industrial
1.732
1.650
0.048
-0.034
Commercial
1.843
1.752
0.116
0.025
C2
C3
C4
VCCL=
1.1 V
VCCL=
1.1 V
VCCL=
1.1 V
2.527 2.758 3.099
2.385 2.595 2.918
-0.142 -0.216 -0.181
-0.284 -0.379 -0.362
C4L
VCCL=
1.1 V
VCCL=
0.9 V
2.997 3.227
2.826 3.068
-0.136 -0.188
-0.307 -0.347
I3
VCCL=
1.1 V
2.811
2.641
-0.173
-0.343
I4
VCCL=
1.1 V
3.146
2.957
0.265
0.076
I4L
VCCL=
1.1 V
VCCL=
0.9 V
3.055 3.260
2.876 3.101
-0.087 -0.230
-0.266 -0.389
Units
ns
ns
ns
ns
Table 1â144 and Table 1â145 list the regional clock timing parameters for EP3SL50
devices.
Table 1â144. EP3SL50 Column Pin Regional Clock Timing Specifications (Part 1 of 2)
Parameter
tCIN
tCOUT
Fast Model
C2
Industrial
1.689
1.689
Commercial
1.669
1.669
VCCL=
1.1 V
2.371
2.371
C3
VCCL=
1.1 V
2.645
2.645
C4
VCCL=
1.1 V
3.004
3.004
C4L
VCCL=
1.1 V
2.719
2.719
VCCL=
0.9 V
3.136
3.136
I3
VCCL=
1.1 V
2.645
2.645
I4
VCCL=
1.1 V
3.009
3.009
I4L
VCCL=
1.1 V
2.719
2.719
VCCL=
0.9 V
3.136
3.136
Units
ns
ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation
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