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EP3SL50 Datasheet, PDF (265/341 Pages) Altera Corporation – Stratix III Device Handbook, Volume 2 | |||
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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1â255
Table 1â119 and Table 1â120 list the EP3SE80 regional clock (RCLK) adder values that
must be added to the GCLK values. Use these adder values to determine I/O timing
when the I/O pin is driven using the regional clock. This applies to all I/O standards
supported by Stratix III devices.
Table 1â119 lists the EP3SE80 column pin delay adders when using the regional clock.
Table 1â119. EP3SE80 Column Pin Delay Adders for Regional Clock
Parameter
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
Fast Model
Industrial
0.251
1.895
-0.069
-1.545
Commercial
0.187
1.982
0.253
-1.367
C2
VCCL=
1.1 V
C3
VCCL=
1.1 V
C4
VCCL=
1.1 V
C4L
VCCL=
1.1 V
VCCL=
0.9 V
I3
VCCL=
1.1 V
I4
VCCL=
1.1 V
I4L
VCCL=
1.1 V
VCCL=
0.9 V
Units
0.308 0.239 0.389 0.103 0.176 0.199 0.102 0.099 0.172 ns
2.923 3.16 3.601 4.28 4.913 3.261 4.491 4.295 4.833 ns
0.551 0.865 0.693 -0.059 -0.119 1.06 0.135 0.066 -0.046 ns
-1.715 -1.587 -1.976 -3.145 -3.116 -1.541 -3.343 -3.027 -3.123 ns
Table 1â120 lists the EP3SE80 row pin delay adders when using the regional clock.
Table 1â120. EP3SE80 Row Pin Delay Adders for Regional Clock
Parameter
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
Fast Model
Industrial
0.014
0.116
0.004
-0.089
Commercial
0.014
0.122
0.003
-0.089
C2
VCCL=
1.1 V
C3
VCCL=
1.1 V
C4
VCCL=
1.1 V
C4L
VCCL=
1.1 V
VCCL=
0.9 V
I3
VCCL=
1.1 V
I4
VCCL=
1.1 V
I4L
VCCL=
1.1 V
VCCL=
0.9 V
Units
0.018 0.005 -0.022 0.0 0.052 -0.004 -0.014 -0.008 0.056 ns
0.192 0.206 0.231 0.217 0.367 0.198 0.223 0.21 0.371 ns
0.029 0.042 0.056 0.039 -0.021 0.047 0.061 0.049 -0.025 ns
-0.145 -0.161 -0.197 -0.169 -0.332 -0.151 -0.186 -0.157 -0.333 ns
EP3SE110 I/O Timing Parameters
Table 1â121 through Table 1â124 list the maximum I/O timing parameters for
EP3SE110 for single-ended I/O standards.
Table 1â121 lists the EP3SE110 column pins input timing parameters for single-ended
I/O standards.
Table 1â121. EP3SE110 Column Pins Input Timing Parameters (Part 1 of 4)
I/O
Standard
Clock
GCLK tsu
th
3.3-V LVTTL
GCLK tsu
PLL th
3.3-V
LVCMOS
GCLK tsu
th
GCLK tsu
PLL th
Fast Model
Industrial
-1.030
1.172
-1.297
1.600
-1.030
1.172
-1.297
1.600
Commercial
-1.006
1.144
-1.267
1.565
-1.006
1.144
-1.267
1.565
C2
VCCL=
1.1 V
-1.454
1.648
-1.831
2.262
-1.454
1.648
-1.831
2.262
C3
VCCL=
1.1 V
-1.613
1.838
-2.023
2.514
-1.613
1.838
-2.023
2.514
C4
VCCL=
1.1 V
C4L
VCCL=
1.1 V
VCCL=
0.9 V
I3
VCCL=
1.1 V
I4
VCCL=
1.1 V
I4L
VCCL=
1.1 V
VCCL=
0.9 V
Units
-1.847 -1.786 -2.148 -1.613 -1.847 -1.786 -2.148 ns
2.093 2.017 2.385 1.838 2.093 2.017 2.385 ns
-2.261 -2.187 -2.655 -2.023 -2.261 -2.187 -2.655 ns
2.793 2.689 3.180 2.514 2.793 2.689 3.180 ns
-1.847 -1.786 -2.148 -1.613 -1.847 -1.786 -2.148 ns
2.093 2.017 2.385 1.838 2.093 2.017 2.385 ns
-2.261 -2.187 -2.655 -2.023 -2.261 -2.187 -2.655 ns
2.793 2.689 3.180 2.514 2.793 2.689 3.180 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2
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