EP3SL50 Datasheet, PDF (256/341 Pages) Altera Corporation – Stratix III Device Handbook, Volume 2

1–246
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–115. EP3SE80 Column Pins Input Timing Parameters (Part 3 of 3)
I/O Standard
DIFFERENTIAL
2.5-V SSTL
CLASS I
DIFFERENTIAL
2.5-V SSTL
CLASS II
Clock
Fast Model
C2
Industrial Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
t_su
GCLK
t_h
GCLK ^tsu
PLL _th
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
-0.840
0.969
1.117
-0.855
-0.840
0.969
1.117
-0.855
-0.881
1.028
1.142
-0.857
-0.881
1.028
1.142
-0.857
-1.289 -1.395 -1.518 -1.460 -1.828 -1.394 -1.510 -1.459 -1.866 ns
1.493 1.625 1.769 1.697 2.070 1.633 1.772 1.706 2.109 ns
1.771 1.998 2.207 2.097 2.011 2.016 2.232 2.116 2.062 ns
-1.350 -1.525 -1.683 -1.603 -1.505 -1.534 -1.696 -1.613 -1.554 ns
-1.289 -1.395 -1.518 -1.460 -1.828 -1.394 -1.510 -1.459 -1.866 ns
1.493 1.625 1.769 1.697 2.070 1.633 1.772 1.706 2.109 ns
1.771 1.998 2.207 2.097 2.011 2.016 2.232 2.116 2.062 ns
-1.350 -1.525 -1.683 -1.603 -1.505 -1.534 -1.696 -1.613 -1.554 ns
Table 1–116 lists the EP3SE80 row pins input timing parameters for differential I/O
standards.
Table 1–116. EP3SE80 Row Pins Input Timing Parameters (Part 1 of 3)
I/O Standard
LVDS
MINI-LVDS
RSDS
DIFFERENTIAL
1.2-V HSTL
CLASS I
DIFFERENTIAL
1.2-V HSTL
CLASS II
Clock
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
Fast Model
C2
Industrial Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
t_su -0.944
t_h 1.077
t_su 0.961
t_h -0.691
t_su -0.944
t_h 1.077
t_su 0.961
t_h -0.691
t_su -0.944
t_h 1.077
t_su 0.961
t_h -0.691
t_su -0.749
t_h 0.875
t_su 1.156
t_h -0.893
t_su -0.749
t_h 0.875
t_su 1.156
t_h -0.893
-0.979
1.130
0.989
-0.700
-0.979
1.130
0.989
-0.700
-0.979
1.130
0.989
-0.700
-0.794
0.936
1.174
-0.894
-0.794
0.936
1.174
-0.894
-1.054 -1.015 -1.154 -1.107 -1.454 -0.975 -1.107 -1.061 -1.493 ns
1.288 1.285 1.447 1.389 1.737 1.257 1.412 1.355 1.777 ns
1.951 2.328 2.533 2.408 2.342 2.387 2.599 2.472 2.394 ns
-1.502 -1.818 -1.968 -1.871 -1.796 -1.862 -2.019 -1.921 -1.844 ns
-1.054 -1.015 -1.154 -1.107 -1.454 -0.975 -1.107 -1.061 -1.493 ns
1.288 1.285 1.447 1.389 1.737 1.257 1.412 1.355 1.777 ns
1.951 2.328 2.533 2.408 2.342 2.387 2.599 2.472 2.394 ns
-1.502 -1.818 -1.968 -1.871 -1.796 -1.862 -2.019 -1.921 -1.844 ns
-1.054 -1.015 -1.154 -1.107 -1.454 -0.975 -1.107 -1.061 -1.493 ns
1.288 1.285 1.447 1.389 1.737 1.257 1.412 1.355 1.777 ns
1.951 2.328 2.533 2.408 2.342 2.387 2.599 2.472 2.394 ns
-1.502 -1.818 -1.968 -1.871 -1.796 -1.862 -2.019 -1.921 -1.844 ns
-1.145 -1.244 -1.343 -1.291 -1.633 -1.246 -1.344 -1.293 -1.677 ns
1.345 1.468 1.587 1.524 1.867 1.479 1.597 1.535 1.912 ns
1.864 2.104 2.344 2.224 2.163 2.120 2.362 2.240 2.210 ns
-1.447 -1.639 -1.828 -1.736 -1.666 -1.644 -1.834 -1.741 -1.709 ns
-1.145 -1.244 -1.343 -1.291 -1.633 -1.246 -1.344 -1.293 -1.677 ns
1.345 1.468 1.587 1.524 1.867 1.479 1.597 1.535 1.912 ns
1.864 2.104 2.344 2.224 2.163 2.120 2.362 2.240 2.210 ns
-1.447 -1.639 -1.828 -1.736 -1.666 -1.644 -1.834 -1.741 -1.709 ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation