EP3SL50 Datasheet, PDF (45/341 Pages) Altera Corporation – Stratix III Device Handbook, Volume 2

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–35
Table 1–37. Output Timing Measurement Methodology for Output Pins (Part 2 of 3)
I/O Standard
1.5-V Differential
HSTL CLASS II
1.2-V Differential
HSTL CLASS I
1.2-V Differential
HSTL CLASS II
LVDS
MINI-LVDS
RSDS
LVDS_E_1R
LVDS_E_3R
R_S
R_D
—
—
—
—
—
—
— 100
— 100
— 100
— 100
120 100
Loading and Termination
Measurement
Point
R_T
R_P
V_CCIO
V_CCPD
V_CC
V_TT
C_L (pF)
V_MEAS (v)
25
— 1.375 2.325 1.02 0.75
0
0.6875
50
— 1.09 2.325 1.02 0.60
0
0.545
25
— 1.09 2.325 1.02 0.60
0
—
— 2.325 2.325 1.02 —
0
—
— 2.325 2.325 1.02 —
0
—
— 2.325 2.325 1.02 —
0
— 120 2.325 2.325 1.02 —
0
— 170 2.325 2.325 1.02 —
0
0.545
1.1625
1.1625
1.1625
1.1625
1.1625
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2