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EP3SL50 Datasheet, PDF (197/341 Pages) Altera Corporation – Stratix III Device Handbook, Volume 2
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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–187
Table 1–94 lists the EP3SL340 row pins output timing parameters for single-ended
I/O standards.
Table 1–94. EP3SL340 Row Pins Output Timing Parameters (Part 1 of 4)
I/O
Standard
Clock
3.3-V
LVTTL
4mA
8mA
GCLK tco
GCLK
PLL
tco
GCLK tco
GCLK
PLL
tco
GCLK tco
12mA
GCLK
PLL
tco
4mA
3.3-V
LVCMOS
8mA
GCLK tco
GCLK
PLL
tco
GCLK tco
GCLK
PLL
tco
3.0-V
LVTTL
4mA
8mA
GCLK tco
GCLK
PLL
tco
GCLK tco
GCLK
PLL
tco
GCLK tco
12mA
GCLK
PLL
tco
3.0-V
LVCMOS
GCLK tco
4mA
GCLK
PLL
tco
GCLK tco
8mA
GCLK
PLL
tco
4mA
GCLK tco
GCLK
PLL
tco
2.5 V
8mA
GCLK tco
GCLK
PLL
tco
GCLK tco
12mA
GCLK
PLL
tco
Fast Model
Industrial Commercial
C2
VCCL=
1.1 V
C3
VCCL=
1.1 V
C4
VCCL=
1.1 V
C4L
VCCL= VCCL=
1.1 V 0.9 V
I3
VCCL=
1.1 V
I4
VCCL=
1.1 V
I4L
VCCL= VCCL=
1.1 V 0.9 V
Units
3.479
3.781 5.469 5.657 6.238 6.095 6.481 5.741 6.370 6.120 6.565 ns
1.562
1.782 2.243 2.285 2.559 2.570 2.578 2.386 2.666 2.671 2.594 ns
3.413
3.681 5.339 5.519 6.093 5.950 6.336 5.628 6.221 6.005 6.416 ns
1.496
1.677 2.113 2.174 2.414 2.425 2.433 2.273 2.517 2.522 2.445 ns
3.334
3.592 5.220 5.398 5.965 5.822 6.208 5.529 6.089 5.905 6.284 ns
1.417
1.575 1.994 2.074 2.286 2.297 2.305 2.174 2.385 2.390 2.313 ns
3.481
3.785 5.477 5.662 6.242 6.099 6.485 5.749 6.374 6.132 6.569 ns
1.564
1.786 2.251 2.291 2.563 2.574 2.582 2.394 2.670 2.675 2.598 ns
3.338
3.596 5.226 5.413 5.971 5.828 6.214 5.541 6.096 5.914 6.291 ns
1.421
1.579 2.000 2.089 2.292 2.303 2.311 2.186 2.392 2.397 2.320 ns
3.440
3.727 5.421 5.610 6.194 6.051 6.437 5.709 6.328 6.086 6.523 ns
1.523
1.728 2.195 2.254 2.515 2.526 2.534 2.354 2.624 2.629 2.552 ns
3.339
3.601 5.269 5.451 6.030 5.887 6.273 5.567 6.164 5.940 6.358 ns
1.422
1.601 2.043 2.112 2.351 2.362 2.370 2.212 2.460 2.464 2.387 ns
3.302
3.563 5.188 5.371 5.942 5.799 6.185 5.499 6.071 5.867 6.265 ns
1.385
1.550 1.961 2.047 2.263 2.274 2.282 2.144 2.367 2.371 2.294 ns
3.361
3.646 5.316 5.503 6.084 5.941 6.327 5.600 6.217 5.976 6.411 ns
1.444
1.647 2.090 2.147 2.405 2.416 2.424 2.245 2.513 2.517 2.440 ns
3.289
3.547 5.161 5.342 5.903 5.760 6.146 5.469 6.031 5.838 6.225 ns
1.372
1.530 1.926 2.018 2.224 2.235 2.243 2.114 2.327 2.331 2.254 ns
3.466
3.763 5.554 5.764 6.366 6.223 6.609 5.841 6.507 6.238 6.701 ns
1.549
1.764 2.328 2.380 2.687 2.698 2.706 2.486 2.803 2.807 2.730 ns
3.381
3.665 5.399 5.601 6.196 6.053 6.439 5.704 6.333 6.093 6.527 ns
1.464
1.666 2.173 2.245 2.517 2.528 2.536 2.349 2.629 2.633 2.556 ns
3.324
3.603 5.288 5.483 6.070 5.927 6.313 5.615 6.203 5.999 6.397 ns
1.407
1.589 2.062 2.159 2.391 2.402 2.410 2.260 2.499 2.503 2.426 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2
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